鈥?/div>
Replaces electromechanical relays, fuses and discrete circuits
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS
廬
technology. Fully protected by embedded protection
functions.
Pin Definitions and Functions
Pin
1,10,
11,12,
15,16,
19,20
3
7
17,18
13,14
4
8
2
6
5,9
Symbol Function
Positive power supply voltage.
Design the
V
bb
wiring for the simultaneous max. short circuit
currents from channel 1 to 2 and also for low
thermal resistance
IN1
Input 1,2,
activates channel 1,2 in case of
IN2
logic high signal
OUT1
Output 1,2,
protected high-side power output
OUT2
of channel 1,2. Design the wiring for the max.
short circuit current
ST1
Diagnostic feedback 1,2
of channel 1,2,
ST2
open drain, low on failure
GND1
Ground 1
of chip 1 (channel 1)
GND2
Ground 2
of chip 2 (channel 2)
N.C.
Not Connected
Pin configuration
(top view)
V
bb
GND1
IN1
ST1
N.C.
GND2
IN2
ST2
N.C.
V
bb
1
2
3
4
5
6
7
8
9
10
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20
19
18
17
16
15
14
13
12
11
V
bb
V
bb
OUT1
OUT1
V
bb
V
bb
OUT2
OUT2
V
bb
V
bb
1
)
With external current limit (e.g. resistor R
GND
=150
鈩?
in GND connection, resistor in series with ST
connection, reverse load current limited by connected load.
Semiconductor Group
1
10.96
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