impedance, twisted-pair (or flat) cable. These
transceivers.
鈩?/div>
relative
to the power supplies; hence, they will not load the
transmission line when the circuit is powered down.
For those circuits with termination resistors, the line
will remain impedance matched when the circuit is
powered down. The driver does not load the line
when it is powered down.
The packaging options that are available for the
dual differential transceivers include a 16-pin DIP; a
16-pin, J-lead SOJ; a 16-pin, gull-wing SOIC; and a
16-pin, narrow-body, gull-wing SOIC.
Two line drivers per package
Logic to convert TTL input logic levels to
differential, pseudo-emitter coupled logic (ECL)
output logic levels
No line loading when V
CC
= 0 V
High output driver for 50
鈩?/div>
loads
200 mA short-circuit current (typical)
2.0 ns maximum propagation delay
<0.2 ns output skew (typical)
s
s
s
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s
Receiver Features
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s
s
Two line receivers per package
High input impedance
鈮?/div>
8 k
鈩?/div>
Logic that converts differential input logic levels to
transistor-transistor logic (TTL) output logic levels
4.0 ns maximum propagation delay
<0.20 V input sensitivity (typical)
鈭?/div>
1.2 V to
+
7.2 V common-mode range
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s
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Common Device Features
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s
Common enable for each driver/receiver pair
Operating temperature range: 鈥?0
擄
C to +125
擄
C
(wider than the 41 Series)
Single 5.0 V
鹵
10% supply
400 Mbits/s maximum data rate
Meets enhanced small device interface (ESDI)
standards
Electrostatic discharge (ESD) performance better
than the 41 Series
Lower power requirement than the 41 Series
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