BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
1M X 8 bit
GENERAL DESCRIPTION
BS62LV8007
鈥?Vcc operation voltage : 2.7V ~ 3.6V
鈥?Very low power consumption :
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.) CMOS standby current
鈥?High speed access time :
-55
55ns
-70
70ns
鈥?Automatic power down when chip is deselected
鈥?Three state outputs and TTL compatible
鈥?Fully static operation
鈥?Data retention supply voltage as low as 1.5V
鈥?Easy expansion with CE1, CE2 and OE options
The BS62LV8007 is a high performance , very low power CMOS Static
Random Access Memory organized as 1,048,576 words by 8 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
1.5uA at 3V/25
o
C and maximum access time of 55ns at 3.0V/85
o
C.
Easy memory expansion is provided by an active LOW chip enable (CE1)
, an active HIGH chip enable (CE2) and active LOW output enable (OE)
and three-state output drivers.
The BS62LV8007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV8007 is available in 48B BGA and 44L TSOP2 packages.
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV8007EC
BS62LV8007FC
BS62LV8007EI
BS62LV8007FI
OPERATING
TEMPERATURE
+0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
RANGE
2.7V ~ 3.6V
2.7V ~ 3.6V
SPEED
( ns )
55ns : 3.0~3.6V
70ns : 2.7~3.6V
( I
CCSB1
, Max )
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
PKG TYPE
Vcc=3V
Vcc=3V
55ns
70ns
55 / 70
55 / 70
5uA
10uA
30mA
31mA
TSOP2-44
24mA BGA-48-0912
TSOP2-44
25mA
BGA-48-0912
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
GND
DQ2
DQ3
NC
NC
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
5
6
A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14
FUNCTIONAL BLOCK DIAGRAM
BS62LV8007EC
BS62LV8007EI
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 X 4096
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
Vdd
Gnd
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
512
Column Decoder
18
Control
Address Input Buffer
2
3
4
A
NC
NC
OE
A0
A1
A2
CE2
B
NC
A3
A4
CE1
NC
NC
8
C
D0
NC
A5
A6
Data
Output
Buffer
8
D4
D
VSS
D1
A17
A7
D5
VCC
E
VCC
D3
D2
VCC
A16
D6
VSS
F
NC
A14
A15
NC
D7
A11A9 A8 A3 A2 A1 A0A10 A19
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
48-ball BGA top view
Brilliance Semiconductor, Inc
. reserves the right to modify document contents without notice.
R0201-BS62LV8007
1
Revision 1.1
Jan.
2004
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