BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
1M X 8 bit
GENERAL DESCRIPTION
BS62LV8003
鈥?Wide Vcc operation voltage : 2.4V ~ 3.6V
鈥?Very low power consumption :
Vcc = 3V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
鈥?High speed access time :
-70
70ns (Max) at Vcc = 3V
-10
100ns (Max) at Vcc = 3V
鈥?Automatic power down when chip is deselected
鈥?Three state outputs and TTL compatible
鈥?Fully static operation
鈥?Data retention supply voltage as low as 1.5V
鈥?Easy expansion with CE1, CE2 and OE options
The BS62LV8003 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 words by 8 bits
and operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.5uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable(CE2) and active LOW output
enable (OE) and three-state output drivers.
The BS62LV8003 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV8003 is available in 44 pin TSOP2 and 48-pin BGA type.
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV8003EC
BS62LV8003BC
BS62LV8003EI
BS62LV8003BI
OPERATING
TEMPERATURE
+0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
RANGE
2.4V ~ 3.6V
2.4V ~ 3.6V
SPEED
( ns )
Vcc=3V
( I
CCSB1
, Max )
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
PKG TYPE
TSOP2-44
BGA-48-0810
TSOP2-44
BGA-48-0810
Vcc=3V
Vcc=3V
70 / 100
70 / 100
3uA
6uA
20mA
25mA
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
GND
DQ2
DQ3
NC
NC
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14
6
FUNCTIONAL BLOCK DIAGRAM
BS62LV8003EC
BS62LV8003EI
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 X 4096
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
Vdd
Gnd
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
512
Column Decoder
18
Control
Address Input Buffer
1
2
3
4
5
A
NC
OE
A0
A1
A2
CE2
8
B
NC
NC
A3
A4
CE1
NC
Data
Output
Buffer
8
C
D0
NC
A5
A6
NC
D4
D
VSS
D1
A17
A7
D5
VCC
E
VCC
D2
VCC
A16
D6
VSS
A11A9 A8 A3 A2 A1 A0A10 A19
F
D3
NC
A14
A15
NC
D7
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
48-Ball CSP top View
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
R0201-BS62LV8003
1
Revision 2.4
April 2002
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