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BS62LV4005PI Datasheet

  • BS62LV4005PI

  • Low Power/Voltage CMOS SRAM 512K X 8 bit

  • 11頁

  • BSI

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BSI
FEATURES
Low Power/Voltage CMOS SRAM
512K X 8 bit
GENERAL DESCRIPTION
BS62LV4005
鈥?Vcc operation voltage : 4.5V ~ 5.5V
鈥?Low power consumption
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I -grade: 50mA (Max.) operating current
1.5uA (Typ.) CMOS standby current
鈥?High speed access time :
-70
70ns (Max.) at Vcc = 5.0V
-55
55ns (Max.) at Vcc = 5.0V
鈥?Automatic power down when chip is deselected
鈥?Three state outputs and TTL compatible
鈥?Fully static operation
鈥?Data retention supply voltage as low as 1.5V
鈥?Easy expansion with CE and OE options
The BS62LV4005 is a high performance, low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with maximum access time of 55/ 70ns
in 5V operation.
Easy memory expansion is provided by active LOW chip
enable (CE), active LOW output enable (OE) and three-state
output drivers.
The BS62LV4005 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4005 is available in the JEDEC standard 32 pin SOP
, TSOP, TSOP II and STSOP .
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV4005SC
BS62LV4005EC
BS62LV4005TC
BS62LV4005STC
BS62LV4005PC
BS62LV4005SI
BS62LV4005EI
BS62LV4005TI
BS62LV4005STI
BS62LV4005PI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
Vcc = 5.0V
( I
CCSB1
, Max )
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
PKG TYPE
SOP-32
TSOP2-32
TSOP-32
STSOP-32
PDIP-32
SOP-32
TSOP2-32
TSOP-32
STSOP-32
PDIP-32
Vcc = 5.0V
Vcc=5.0V
+0
O
C to +70
O
C
4.5V ~ 5.5V
55 / 70
15uA
45mA
-40
O
C to +85
O
C
4.5V ~ 5.5V
55 / 70
25uA
50mA
PIN CONFIGURATIONS
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
BS62LV4005SC
9
BS62LV4005SI
10
BS62LV4005EC
BS62LV4005EI
11
BS62LV4005PC
12
BS62LV4005PI
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
FUNCTIONAL BLOCK DIAGRAM
鈥?/div>
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 X 2048
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
256
Column Decoder
16
CE
WE
OE
Vdd
Gnd
A11 A9 A8 A3 A2 A1 A0 A10
Control
Address Input Buffer
8
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV4005TC
BS62LV4005STC
BS62LV4005TI
BS62LV4005STI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
Data
Output
8
Brilliance Semiconductor Inc
.
reserves the right to modify document contents without notice.
R0201-BS62LV4005
鈥?/div>
1
Revision 2.4
April 2002

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