BSI
FEATURES
Ultra Low Power/Voltage CMOS SRAM
128K X 16 bit
BS616UV2019
鈥?Wide Vcc operation voltage :
C-grade: 1.8V~3.6V
I-grade: 1.9V~3.6V
(Vcc_min.=1.65V at 25
o
C)
鈥?Ultra low power consumption :
Vcc = 2.0V
C-grade: 8mA (Max.) operating current
I -grade: 10mA (Max.) operating current
0.20uA (Typ.) CMOS standby current
Vcc = 3.0V
C-grade: 11mA (Max.) operating current
I -grade: 13mA (Max.) operating current
0.30uA (Typ.) CMOS standby current
鈥?High speed access time :
-85
85ns (Max.)
-10
100ns (Max.)
鈥?Automatic power down when chip is deselected
鈥?Three state outputs and TTL compatible
鈥?Fully static operation
鈥?Easy expansion with CE and OE options
鈥?I/O Configuration x8/x16 selectable by LB and UB pin
鈥?Data retention supply voltage as low as 1.0V
DESCRIPTION
The BS616UV2019 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.2uA at 2.0V /25
o
C and maximum access time of 85ns at 85
o
C.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616UV2019 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV2019 is available in DICE form, JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
PRODUCT FAMILY
PRODUCT
FAMILY
BS616UV2019DC
BS616UV2019TC
BS616UV2019AC
BS616UV2019DI
BS616UV2019TI
BS616UV2019AI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
C-grade:1.8~3.6V
I-grade:1.9~3.6V
( I
CCSB1
, Max )
Vcc=3.0V
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
PKG TYPE
DICE
TSOP1-48
BGA-48-0608
DICE
TSOP1-48
BGA-48-0608
+0
O
C to +70
O
C
-40
O
C to +85
O
C
1.8V ~3.6V
1.9V ~ 3.6V
85/100
85/100
3.0uA
2.0uA
11mA
8mA
10mA
5.0uA
3.0uA
13mA
PIN CONFIGURATIONS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
CE2
NC
/UB
/LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
48
47
46
A16
NC
VSS
IO15
IO7
IO14
IO6
IO13
IO5
IO12
IO4
VCC
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
/OE
VSS
/CE
A0
BLOCK DIAGRAM
A8
A13
A15
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
9
10
13
16
17
20
Row
Decoder
1024
Memory Array
1024 x 2048
BS616UV2019TC
BS616UV2019TI
37
2048
DQ0
16
Data
Input
Buffer
16
Column I/O
27
24
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
N.C.
2
OE
UB
D10
D11
D12
D13
N.C.
A8
3
A0
A3
A5
N.C.
N.C.
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
D1
D3
D4
D5
WE
A11
6
N.C.
D0
D2
VCC
VSS
D6
D7
N.C.
25
.
.
.
.
DQ15
.
.
.
.
Write Driver
Sense Amp
128
Column Decoder
16
Data
Output
16
Buffer
CE2 ,CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
48-ball BGA top view
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS616UV2019
1
Revision 1.1
Jan.
2004
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