BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
DESCRIPTION
BS616LV8022
鈥?Very low operation voltage : 2.4 ~ 5.5V
鈥?Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I-grade : 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
鈥?High speed access time :
-70
70ns (Max.) at Vcc= 3.0V
-10 100ns (Max.) at Vcc= 3.0V
鈥?Automatic power down when chip is deselected
鈥?Three state outputs and TTL compatible
鈥?Fully static operation
鈥?Data retention supply voltage as low as 1.5V
鈥?Easy expansion with CE1, CE2 and OE options
鈥?I/O Configuration x8/x16 selectable by CIO, LB and UB pin
The BS616LV8022 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.5uA and maximum access time of 70/100ns in 3.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV8022 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8022 is available in 48-pin BGA type.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=3.0V
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
(I
CC
, Max)
PKG TYPE
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
BS616LV8022BC +0
O
C to +70
O
C
BS616LV8022BI -40
O
C to +85
O
C
2.4V ~ 5.5V
2.4V ~ 5.5V
70 / 100
70 / 100
3uA
6uA
30uA
100uA
20mA
25mA
45mA
50mA
BGA
-48-0810
BGA
-48-0810
PIN CONFIGURATIONS
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
A18
2
OE
UB
D10
D11
D12
D13
CIO
.
A8
3
A0
A3
A5
A17
VSS
A14
A 12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
D1
D3
D4
D5
6
CE2
D0
D2
VCC
VSS
D6
D7
SAE.
BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
A17
A7
A6
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 4096
4096
D0
16(8)
Data
Input
Buffer
16(8)
Column I/O
.
.
.
.
D15
CE1
CE2
WE
OE
UB
LB
CIO
Vdd
Vss
.
.
.
.
Write Driver
16(8)
Sense Amp
256(512)
Column Decoder
16(8)
Data
Output
Buffer
16(18)
Control
Address Input Buffer
WE
A11
A16 A0 A1 A2 A3 A4 A5 A18 (SAE)
48-Ball CSP top View
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
R0201-BS616LV8022
1
Revision 2.4
April 2002
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