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BS616LV8011AI Datasheet

  • BS616LV8011AI

  • Very Low Power/Voltage CMOS SRAM 512K X 16 bit

  • 193.34KB

  • 9頁(yè)

  • BSI

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BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
512K X 16 bit
DESCRIPTION
BS616LV8011
鈥?Very low operation voltage : 2.7 ~ 3.6V
鈥?Very low power consumption :
Vcc = 3.0V C-grade: 40mA (Max.) operating current
I-grade : 50mA (Max.) operating current
1uA (Typ.) CMOS standby current
鈥?High speed access time :
-70
70ns (Max.) at Vcc=3.0V
-10
100ns (Max.) at Vcc=3.0V
鈥?Automatic power down when chip is deselected
鈥?Three state outputs and TTL compatible
鈥?Fully static operation
鈥?Data retention supply voltage as low as 1.5V
鈥?Easy expansion with CE1,CE2 and OE options
The BS616LV8011 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE1,CE2) and active LOW output enable(OE) and three-state
output drivers.
The BS616LV8011 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8011 is available in 48-pin BGA package.
PRODUCT FAMILY
SPEED
(ns)
Vcc=3.0V
PRODUCT FAMILY
OPERATING
TEMPERATURE
+0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
RANGE
2.7V ~ 3.6V
2.7V ~ 3.6V
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
Vcc=3.0V
(I
CC
, Max)
Vcc=3.0V
PKG TYPE
BS616LV8011AC
BS616LV8011AI
70 / 100
70 / 100
16uA
24uA
40mA
50mA
BGA-48-0608
BGA-48-0608
PIN CONFIGURATIONS
1
A
B
C
D
E
F
G
H
X
D8
D9
VSS
VCC
D14
D15
A18
2
OE
X
D10
D11
D12
D13
NC
.
A8
3
A0
A3
4
A1
A4
5
A2
6
CE2
D0
D2
VCC
VSS
D6
BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 4096
CE1
D1
D3
D4
D5
A5
A17
Vss
A14
A12
A9
A6
A7
A16
A15
A 13
A10
4096
D0
16
Data
Input
Buffer
16
Column I/O
.
.
.
.
D15
.
.
.
.
Write Driver
Sense Amp
256
Column Decoder
16
Data
Output
16
Buffer
CE1
CE2
16
Control
Address Input Buffer
WE
A11
D7
NC
.
OE
WE
A11 A10 A9 A8 A7 A6 A5 A18
Vcc
Gnd
48-Ball CSP top View
X: Don鈥檛 care
Brilliance Semiconductor Inc
.
reserves the right to modify document contents without notice.
R0201-BS616LV8011
1
Revision 2.3
April 2002

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