bq2502
Features
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Power monitoring, backup supply,
and switching for 3V battery-
backup applications
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Write-protect control
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Input decoder for control of up to
2 banks of SRAM
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3-volt backup power output
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Internal 130mAh lithium-coin
cell
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Reset output for system power-on
reset
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L e s s t ha n 10n s chi p-e nable
propagation delay
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5% or 10% supply operation
Integrated Backup Unit
General Description
The CMOS bq2502 Integrated Backup
Unit provides all the necessary func-
tions for converting one or two
banks of standard CMOS SRAM
into nonvolatile read/write memory.
A precision comparator monitors the 5V
V
CC
input for an out-of-tolerance condi-
tion. When out of tolerance is detected,
the two conditioned chip-enable outputs
are forced inactive to write-protect both
banks of SRAM.
Power for the external SRAMs is
switched from the V
CC
supply to the
internal battery-backup supply as
V
C C
decays. On a subsequent
power-up, the V
OUT
supply is auto-
matically switched from the internal
lithium supply to the V
CC
supply.
The external SRAMs are write-pro-
tected until a power-valid condition
exists. The reset output provides
power-fail and power-on resets for the
system.
During power-valid operation, the
input decoder selects one of two
banks of SRAM.
The internal lithium cell is initially
electrically isolated, protecting the
battery from accidental discharge.
Connection to the battery is made
only after the first application of
V
CC
.
Pin Connections
VOUT
NC
A
NC
THS
VSS
1
2
3
4
5
6
12
11
10
9
8
7
VCC
CE
CECON1
CECON2
NC
RST
Pin Names
V
OUT
RST
THS
CE
CE
CON1
,
CE
CON2
A
NC
V
CC
V
SS
Supply output
Reset output
Threshold select input
chip-enable active low input
Conditioned chip-enable outputs
Bank select input
No connect
5-volt supply input
Ground
12-Pin 600-mil DIP Module
PN250201.eps
Functional Description
Two banks of CMOS static RAM can be battery-backed
using the V
OUT
and conditioned chip-enable output pins
from the bq2502. As the voltage input V
CC
slews down
during a power failure, the two conditioned chip-enable
outputs, CE
CON1
and CE
CON2
, are forced inactive
independent of the chip-enable input CE.
This activity unconditionally write-protects external SRAM
as V
CC
falls to an out-of-tolerance threshold V
PFD
. V
PFD
is
selected by the threshold-select input pin, THS. If THS is
tied to V
SS
, the power-fail detection occurs at 4.62V typical
for 5% supply operation.
Apr. 1991
If THS is tied to V
OUT
, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to V
SS
or V
OUT
for proper operation.
If a memory access is in process to any of the two exter-
nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time t
WPT
(150碌s maximum), the two chip-enable
outputs are unconditionally driven high, write-protecting
the controlled SRAMs.
1
1
2
3
4
5
6
7
8
9
10
11
12
