bq2202
SRAM NV Controller With Reset
Features
General Description
The CMOS bq2202 SRAM Nonvolatile
Controller With Reset provides all the
necessary functions for converting one
or two banks of standard CMOS
SRAM into nonvolatile read/write
memory.
A precision comparator monitors the
5V V
CC
input for an out-of-tolerance
condition. When out-of-tolerance is
de t e ct ed , t he t wo co n diti on e d
chip-enable outputs are forced inac-
tive to write-protect both banks of
SRAM.
Power for the external SRAMs is
switched from the V
CC
supply to the
battery-backup supply as V
CC
de-
cays. On a subsequent power--up, the
V
OUT
supply is automatically
switched from the backup supply to
the V
CC
supply. The external SRAMs
are write-protected until a power-
valid condition exists. The reset out-
put provides power-fail and power-on
resets for the system.
During power-valid operation, the
input decoder selects one of two
banks of SRAM.
盲
Power monitoring and switching
for nonvolatile control of SRAMs
盲
Write-protect control
盲
Input decoder allows control of
up to 2 banks of SRAM
盲
3-volt primary cell input
盲
3-volt rechargeable battery in-
put/output
盲
Reset output for system power-on
reset
盲
L e s s t ha n 10n s chip e nabl e
propagation delay
盲
5% or 10% supply operation
Pin Connections
Pin Names
V
OUT
RST
THS
CE
CE
CON1
,
CE
CON2
A
BC
P
BC
S
NC
V
CC
V
SS
Supply output
Reset output
Threshold select input
Chip enable active low input
Conditioned chip enable outputs
Bank select input
3V backup supply input
3V rechargeable backup supply input/output
No connect
+5 volt supply input
Ground
VOUT
BCP
NC
A
NC
NC
THS
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
BCS
CE
CECON1
CECON2
NC
RST
NC
16-Pin Narrow DIP or SOIC
PN220201.eps
Functional Description
Two banks of CMOS static RAM can be battery-backed
using the V
OUT
and conditioned chip-enable output pins
from the bq2202. As the voltage input V
CC
slews down
during a power failure, the two conditioned chip enable
outputs, CE
CON1
and CE
CON2
, are forced inactive
independent of the chip enable input CE.
This activity unconditionally write-protects external
SRAM as V
CC
falls to an out-of-tolerance threshold
V
PFD
. V
PFD
is selected by the threshold select input pin,
THS. If THS is tied to V
SS
, the power-fail detection oc-
curs at 4.62V typical for 5% supply operation.
Sept. 1997 D
If THS is tied to V
CC
, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to V
SS
or V
CC
for proper operation.
If a memory access is in process to any of the two exter-
nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time t
WPT
(150碌sec maximum), the two chip en-
able outputs are unconditionally driven high, write-
protecting the controlled SRAMs.
1
1
2
3
4
5
6
7
8
9
10
