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BCM8020 Datasheet

  • BCM8020

  • 8-CHANNEL MULTIRATE 1.0-3.2-GBPS TRANSCEIVER

  • 2頁(yè)

  • ETC

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BCM8020
8-CHANNEL MULTIRATE 1.0鈥?.2-GBPS TRANSCEIVER
FEATURES
鈥?/div>
8 independent transceivers supporting multiple data rates
from 1.0 Gbps to 3.2 Gbps including 1.06 Gbps, 1.25 Gbps, 2.12
Gbps, 2.488 Gbps, 2.5 Gbps, 2.667 Gbps, 3.125 Gbps, and
3.1875 Gbps
Multiconfigurable to support various operating modes
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Eight Independent 1.0 to 3.2-Gbps SerDes Channels
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Dual quad 1.0 to 3.2-Gbps SerDes with channel alignment
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SerDes-to-SerDes retimer mode: CML and XAUI interfaces
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Full mesh switching maps any XAUI port to any XGMII port
for full redundancy on both transmitter and receiver
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Selectable TBI DDR/RTBI or XGMII parallel interface
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HSTL (1.8V or 1.5V) and SSTL_2 parallel interface
Low power dissipation
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Less than 300 mW per transceiver channel including I/O
High performance programmable Rx equalization and Tx pre-
emphasis
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Tx pre-emphasis for interoperability with CML SerDes
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Rx equalization for copper interconnects
Enhanced test capability
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Serial and parallel loopback, BIST, 10G BERT, and random
Ethernet packet generation
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IEEE (1149.1) JTAG
Compact 23-mm 脳 23-mm package with no external
components required
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No requirement for heat sink or airflow
SUMMARY OF BENEFITS
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One device supports a variety of applications including
Gigabit Ethernet, 1脳 and 2脳 Fibre Channel, OC-48 SONET
(with/without FEC), Infiniband, 10-Gigabit Ethernet, 10-
Gigabit Fibre Channel, or others.
Flexible architecture supports programmable configurations
enabling an aggregate data transfer rate of over 20 Mbps.
Built-in redundancy mode provides high availability to
support critical line side or backplane applications. The high-
speed to high-speed retimer mode extends the use of longer
traces on line card designs.
Advanced 0.13-碌 CMOS process technology provides
unparalleled performance while achieving the lowest possible
power consumption.
Eases linecard designs to allow for multiple connectors or low-
cost PCB materials such as FR4.
Drive PMD devices or back-plane directly with no external
clean-up circuit required.
Simplifies manufacturability with integrated Built-in self-test
(BIST), high-speed and low-speed loopbacks, and
programmable PRBS generator/checker.
Decreases complexity and reduces board space on multi-
channel line-card designs.
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Tx
BACKPLANE
BCM8702
Rx
BCM8020
ASIC/MAC
BCM8020
2脳 XENPAK
Tx
BCM8702
2脳 XAUI
2脳 XGMII/TBI
2脳 XGMII/TBI
2脳 XAUI
Rx
2 Independent Quad SerDes Application Diagram

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