鈥?/div>
Two 64-bit MIPS CPUs, scalable from
鈥?Quad-issue in order pipeline; dual execute, dual memory pipes
鈥?Enhanced skew pipeline enables zero load-to-use penalty
鈥?32-KB instruction cache, 32-KB data cache
鈥?Advanced branch predictors
鈥?Connects the CPUs, L2 cache, memory controller and I/O bridges
鈥?Runs at half the CPU core frequency; 256 bits wide
鈥?512 KB, shared by both CPUs
鈥?4-way associative, ECC protected
鈥?Ways can be removed to provide fast on-chip RAM
鈥?Two channels, each with a 64-bit data bus plus optional ECC
鈥?Runs up to 200 MHz clock rate, 400 MHz data rate
鈥?Support for DDR SDRAM, SGRAM, and FCRAM
鈥?Three 10/100/1000 Ethernet MACs; 802.3 compliant
鈥?Option to configure MACs into packet FIFOs
鈥?Up to two packet FIFOs each capable of OC-48 data rates
鈥?32 bits, 33/66 MHz (PCI 2.2)
鈥?Host bridge or target device
TM
鈥?/div>
Industry-leading performance
鈥?/div>
Fast, on-chip multiprocessor bus
鈥?/div>
On-chip L2 cache
鈥?/div>
Low power dissipation of 8鈥?0W (@ 800 MHz)
鈥?/div>
High functional integration
Programming
鈥?/div>
Instruction Setease and flexibility based on MIPS64
Architecture (ISA)
鈥?/div>
Scalable multiprocessor chip and system architecture
鈥?/div>
Broad tools and system software support
For additional information on
鈥?/div>
evaluation boards, refer to the the BCM1250and
BCM91250A
BCM91250E product briefs
*Based on internal Broadcom benchmark, using BCM1250 for
standard IPv4 L3 look-up/switching.
鈥?Processing speed of up to 10 Mpps*
鈥?128 Gbps on-chip bus bandwidth; 50 Gbps memory
bandwidth, 30 Gbps total I/O bandwidth
鈥?/div>
DDR memory controller
TA R G E T
A P P L I C AT I O N S
鈥?/div>
High-speed packet interfaces
鈥?/div>
PCI interface
Due to the BCM1250's world-class performance, power
efficiency and integration, the processor is ideal for a
broad variety of applications including:
鈥?Enterprise workgroup and backbone switches
鈥?VPN switches/routers
鈥?Multiservice access concentrators
鈥?SAN routers/gateway/switches
鈥?IP services/subscriber management platforms
鈥?Web-server switches
鈥?High-end firewall/intrusion detection devices
鈥?Wireless basestations
鈥?/div>
HyperTransport
(formerly LDT) I/O interface
鈥?/div>
Integrated system I/O
鈥?Complies with HyperTransport
TM
standard for high-speed I/O
fabric
鈥?500-MHz clock rate, double data rate, for 600 MHz CPUs;
600-MHz clock rate for 800 MHz CPUs
鈥?Peak bandwidth of 9.6 Gbps in each direction @ 600 MHz
鈥?Supports double-ended fabrics (to link two BCM1250s)
鈥?Generic I/O for direct connect to boot ROM, flash
鈥?Two SMBus serial configuration interfaces
鈥?PCMCIA control interface
鈥?Two serial interfaces
Example: Packet Processing Blade
BCM5840
2,400 Mbps
IPSec
BCM5615
24-10/100
+2-Gigabit
Ports
PCI
SMII
24
10/100
Ports
BCM5238
BCM5238
FPGA
HyperTransport
鈥?/div>
Extensive, on-chip debug features
鈥?/div>
8鈥?0W power dissipation @ 800 MHz
鈥?/div>
Support for leading operating systems including
VxWorks , Linux and NetBSD
鈥?/div>
Evaluation board platform available with tools,
廬
廬
BCM5238
SGMII
4
10/100
/1000
Ports
GMII
BCM5404
BCM5680
8-Port
10/100/1000
BASE-T
Aggregation,
L2/L3 Switching
BCM
1250
BCM
1250
DDR
DRAM
GMII
DDR
DRAM
firmware and software drivers
Deep Packet
Look-up,
L4-L7 Processing
BCM1250相關(guān)型號PDF文件下載
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英文版
VOICE OVER IP ETHERNET CPE ENGINE
ETC
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英文版
VOICE OVER IP ETHERNET CPE ENGINE
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英文版
THE MOST HIGHLY INTEGRATED SILICON SOLUTION FOR FEATURE ENGA...
ETC
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THE MOST HIGHLY INTEGRATED SILICON SOLUTION FOR FEATURE ENGA...
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VOICE OVER IP CPE ENGINE
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ENTERPRISE IP PHONE CHIP
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SINGLE PORT ENTERPRISE IP PHONE CHIP
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SINGLE PORT ENTERPRISE IP PHONE CHIP
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HIGH-PERFORMANCE MIPS CONTROL PROCESSOR
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MOBILE VOIP PROCESSOR
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HIGH PERFORMANCE INTEGRATED 64 BIT MULTIPROCESSOR
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HIGH PERFORMANCE INTEGRATED 64 BIT MULTIPROCESSOR
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DUAL-CORE 64-BIT MIPS PROCESSOR
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DUAL-CORE 64-BIT MIPS PROCESSOR
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DUAL-CORE 64-BIT MIPS PROCESSOR
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DUAL-CORE 64-BIT MIPS PROCESSOR
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CALISTO VoP SOLUTION
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CALISTO VoP SOLUTION
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CALISTO TEST AND REFERENCE PLATFORM
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CALISTO VoP SOLUTION
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