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BBT3821LP-JH Datasheet

  • BBT3821LP-JH

  • Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

  • 1107.43KB

  • 75頁

  • INTERSIL   INTERSIL

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廬
BBT3821
Data Sheet
July 20, 2005
FN7483.2
Octal 2.488Gbps to 3.187Gbps/
Lane Retimer
Features
鈥?8 Lanes of Clock & Data Recovery and Retiming; 4 in
Each Direction
鈥?Differential Input/Output
鈥?Wide Operating Data Rate Range: 2.488Gbps to
3.1875Gbps, and 1.244Gbps to 1.59325Gbps
鈥?Ultra Low-Power Operation (195mW typical per lane,
1550mW typical total consumption)
鈥?Low Power Version Available for LX4 Applications
鈥?17mm Square Low Profile 192 pin 1.0mm Pitch EBGA
Package
鈥?Compliant to the IEEE 802.3 10GBASE-LX4(WWDM),
10GBASE-CX4, and XAUI Specifications
鈥?Reset Jitter Domain
鈥?Meets 802.3ae and 802.3ak Jitter Requirements with
Significant Margin
鈥?Received Data Aligned to Local Reference Clock for
Retransmission
鈥?Increase Driving Distance
鈥?LX4: Up to 40 inches of FR-4 Traces or 500 Meters of
MMF Fiber at 3.1875Gbps
鈥?CX4: Over 15 meters of Compatible Cable
鈥?Deskewing and Lane-to-Lane Alignment
鈥?0.13mm Pure-Digital CMOS Technology
鈥?1.5V Core Supply, Control I/O 2.5V Tolerant
鈥?Clock Compensation
鈥?Tx/Rx Rate Matching via IDLE Insertion/Deletion up to
鹵100ppm Clock Difference
鈥?Receive Signal Detect and 16 Levels of Receiver
Equalization for Media Compensation
鈥?CML CX4 Transmission Output with 16 Settable Levels of
Pre-Emphasis, Eight on XAUI Side
鈥?Single-Ended or Differential Input Lower-Speed Reference
Clock
鈥?Ease of Testing
鈥?Complete Suite of Ingress-Egress Loopbacks
鈥?Full 802.3ae Pattern Generation and Test, including
CJPAT & CRPAT
鈥?PRBS (both 2
23
-1 and 13458 byte) Built-In Self Tests,
Error Flags and Count Output
鈥?JTAG and AC-JTAG Boundary Scan
鈥?Long Run Length (512 bit) Frequency Lock Ideal for
Proprietary Encoding Schemes
鈥?Extensive Configuration and Status Reporting via 802.3
Clause 45 Compliant MDC/MDIO Serial Interface
鈥?Automatic Load of BBT3821 Control and all XENPAK
Registers from EEPROM or DOM Circuit
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Egress 3
Egress 2
Egress 1
Egress 0
Ingress 3
Ingress 2
Ingress 1
Ingress 0
Receive
Parallel
Data
RX0N
RX0P
Clock &
Data
Recovery
Deserializer
and Comma
Detector
8B/10B
Decoder
Receive
FIFO
8B/10B
Encoder
& Mux
TX0N
TX0P
RFCP
RFCN
Clock Multiplier
3.125G
MDIO MDC
MDIO/MDC
Register File
I
2
C Interface
SCL
SDA
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

BBT3821LP-JH 產(chǎn)品屬性

  • 90

  • 集成電路 (IC)

  • 時(shí)鐘/計(jì)時(shí) - 專用

  • -

  • 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器

  • 無

  • -

  • CML

  • CML，CMOS

  • 1

  • 8:8

  • 是/是

  • 1.59Gbps

  • 1.3 V ~ 2.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 192-EBGA

  • 192-EBGA-B（17x17）

  • 托盤

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