音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

BBT3821LP-JH Datasheet

  • BBT3821LP-JH

  • Octal 2.488Gbps to 3.187Gbps/ Lane Retimer

  • 75頁

  • INTERSIL   INTERSIL

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

廬
BBT3821
Data Sheet
July 20, 2005
FN7483.2
Octal 2.488Gbps to 3.187Gbps/
Lane Retimer
Features
鈥?8 Lanes of Clock & Data Recovery and Retiming; 4 in
Each Direction
鈥?Differential Input/Output
鈥?Wide Operating Data Rate Range: 2.488Gbps to
3.1875Gbps, and 1.244Gbps to 1.59325Gbps
鈥?Ultra Low-Power Operation (195mW typical per lane,
1550mW typical total consumption)
鈥?Low Power Version Available for LX4 Applications
鈥?17mm Square Low Profile 192 pin 1.0mm Pitch EBGA
Package
鈥?Compliant to the IEEE 802.3 10GBASE-LX4(WWDM),
10GBASE-CX4, and XAUI Specifications
鈥?Reset Jitter Domain
鈥?Meets 802.3ae and 802.3ak Jitter Requirements with
Significant Margin
鈥?Received Data Aligned to Local Reference Clock for
Retransmission
鈥?Increase Driving Distance
鈥?LX4: Up to 40 inches of FR-4 Traces or 500 Meters of
MMF Fiber at 3.1875Gbps
鈥?CX4: Over 15 meters of Compatible Cable
鈥?Deskewing and Lane-to-Lane Alignment
鈥?0.13mm Pure-Digital CMOS Technology
鈥?1.5V Core Supply, Control I/O 2.5V Tolerant
鈥?Clock Compensation
鈥?Tx/Rx Rate Matching via IDLE Insertion/Deletion up to
鹵100ppm Clock Difference
鈥?Receive Signal Detect and 16 Levels of Receiver
Equalization for Media Compensation
鈥?CML CX4 Transmission Output with 16 Settable Levels of
Pre-Emphasis, Eight on XAUI Side
鈥?Single-Ended or Differential Input Lower-Speed Reference
Clock
鈥?Ease of Testing
鈥?Complete Suite of Ingress-Egress Loopbacks
鈥?Full 802.3ae Pattern Generation and Test, including
CJPAT & CRPAT
鈥?PRBS (both 2
23
-1 and 13458 byte) Built-In Self Tests,
Error Flags and Count Output
鈥?JTAG and AC-JTAG Boundary Scan
鈥?Long Run Length (512 bit) Frequency Lock Ideal for
Proprietary Encoding Schemes
鈥?Extensive Configuration and Status Reporting via 802.3
Clause 45 Compliant MDC/MDIO Serial Interface
鈥?Automatic Load of BBT3821 Control and all XENPAK
Registers from EEPROM or DOM Circuit
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Egress 3
Egress 2
Egress 1
Egress 0
Ingress 3
Ingress 2
Ingress 1
Ingress 0
Receive
Parallel
Data
RX0N
RX0P
Clock &
Data
Recovery
Deserializer
and Comma
Detector
8B/10B
Decoder
Receive
FIFO
8B/10B
Encoder
& Mux
TX0N
TX0P
RFCP
RFCN
Clock Multiplier
3.125G
MDIO MDC
MDIO/MDC
Register File
I
2
C Interface
SCL
SDA
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

BBT3821LP-JH 產(chǎn)品屬性

  • 90

  • 集成電路 (IC)

  • 時鐘/計時 - 專用

  • -

  • 時鐘和數(shù)據(jù)恢復（CDR），多路復用器

  • 無

  • -

  • CML

  • CML，CMOS

  • 1

  • 8:8

  • 是/是

  • 1.59Gbps

  • 1.3 V ~ 2.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 192-EBGA

  • 192-EBGA-B（17x17）

  • 托盤

BBT3821LP-JH相關型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網(wǎng)站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！