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18 Bit SSTL_2 Termination Sets.
Compliant to JEDEC Std. 8-9B.
Superior High Frequency Performance.
Minimal stray capacitance and inductance are achieved by placing resistors and BGA
termination on the same side of ceramic substrate.
The device can be easily surface mounted using automatic Pick and
Place equipment.
ELECTRICAL
PARAMETER (Maximum)
Resistance, Nominal
Absolute Tolerance
Temperature Coefficient of
Resistance
Interlead Capacitance, Maximum
Operation Temperature
Power Rating (per package)
LIMIT
Various
1
200
0.1
-55 to 125
1
UNITS
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%
ppm/擄C
pF
擄C
Watt
Schmatic
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