鈥?/div>
250ps Propagation Delay
High Bandwidth Output Transitions
Operating Range of 3.0V to 5.5V
Internal Input Pulldown Resistors
Direct Replacement For ON
Semiconductor MC10EL16, MC100EL16,
& MC100LVEL16
PACKAGE
SOIC 8
SOIC 8
TSSOP 8
TSSOP 8 RoHS
Compliant / Lead
(Pb) Free
TSSOP 8
TSSOP 8 RoHS
Compliant / Lead
(Pb) Free
1
2
ARIZONA MICROTEK, INC.
ECL/PECL Differential Receiver
PACKAGE AVAILABILITY
PART NUMBER
AZ10LVEL16D
AZ100LVEL16D
AZ10LVEL16T
AZ10LVEL16T+
AZ100LVEL16T
AZ100LVEL16T+
MARKING
AZM10
LVEL16
AZM100
LVEL16
AZT
LV16
AZT+
LV16
AZH
LV16
AZH+
LV16
NOTES
1,2
1,2
1,2
1,2
1,2
1,2
DESCRIPTION
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: 鈥淵鈥?or 鈥淵Y鈥?for year followed by 鈥淲W鈥?for week on
underside of part.
The AZ10/100LVEL16 is a differential receiver. The device is functionally equivalent to the E116 device with
higher performance capabilities. With output transition times significantly faster than the E116, the LVEL16 is
ideally suited for interfacing with high frequency sources.
The LVEL16 provides a V
BB
output for single-ended use or a DC bias reference for AC coupling to the
爐
device. For single-ended input applications, the V
BB
reference should be connected to one side of the D/D
differential input pair. The input signal is then fed to the other D/D input. The V
BB
pin can support 1.5 mA
爐
sink/source current. When used, the V
BB
pin should be bypassed to ground via a 0.01
碌F
capacitor.
Under open input conditions internal input clamps will force the Q output LOW.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
PIN
D, D
爐
Q, Q
爐
V
BB
V
CC
V
EE
NC
FUNCTION
Data Inputs
Data Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
NC
1
8
V
CC
D
2
7
Q
D
3
6
Q
V
BB
4
5
V
EE
1630 S. STAPLEY DR., SUITE 125
鈥?/div>
MESA, ARIZONA 85204
鈥?/div>
USA
鈥?/div>
(480) 962-5881
鈥?/div>
FAX (480) 890-2541
www.azmicrotek.com
1
2
3
4
5
6
