will override the on-chip pull-down resistor. The AZ100LVEL16VR also provides a V
and 470鈩?/div>
internal bias resistors from D to V
BB
and D to V
BB
. The V
BB
pin can support 1.5mA sink/source current. Bypassing
爐
V
BB
to ground with a 0.01
碌F
capacitor is recommended.
Outputs Q/Q each have a selectable on-chip pull-down current source. See truth table below for current source
爐
functions. External resistors may also be used to increase pull-down current to a maximum total of 25mA.
Outputs Q
HG
/Q
HG
each have an optional on-chip pull-down current source of 10mA. When pad/pin V
EEP
is left
爐
open (NC), the output current sources are disabled and the Q
HG
/Q
HG
operate as standard PECL/ECL. When V
EEP
is
爐
connected to V
EE
, the current sources are activated. The Q
HG
/Q
HG
pull-down current can be decreased, by using a
爐
resistor to connect from V
EEP
to V
EE
.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 125
鈥?/div>
MESA, ARIZONA 85204
鈥?/div>
USA
鈥?/div>
(480) 962-5881
鈥?/div>
FAX (480) 890-2541
www.azmicrotek.com
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