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ATR0620 Datasheet

  • ATR0620

  • GPS BASEBAND PROCESSOR

  • 15頁(yè)

  • ATMEL   ATMEL

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Features
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Utilizes the ARM7TDMI
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ARM
廬
Thumb
廬
Processor Core
鈥?High-performance 32-bit RISC Architecture
鈥?High-density 16-bit Instruction Set
鈥?Embedded ICE (In-circuit Emulation)
128 Kbytes Internal RAM
Fully Programmable External Bus Interface (EBI)
鈥?Maximum External Address Space of 64 MB
鈥?Up to Four Chip Selects
鈥?Software Programmable 8-/16-bit External Data Bus
16-channel GPS Correlator
鈥?Accuracy: TBD
鈥?Time to First Fix: TBD
8-channel Peripheral Data Controller (PDC)
8-level Priority, Individually Maskable, Vectored Interrupt Controller
鈥?Three External Interrupts
20 Programmable I/O Lines
Three USARTs
鈥?Two Dedicated Peripheral Data Controller (PDC) Channels per USART
Master/Slave SPI Interface
鈥?Two Dedicated Peripheral Data Controller (PDC) Channels
鈥?8- to 16-bit Programmable Data Length
鈥?Four External Slave Chip Selects
Programmable Watchdog Timer
Power Management Controller (PMC)
鈥?CPU and Peripherals Can Be Deactivated Individually
Clock Manager (CLM)
鈥?Geared Master Clock to Reduce Power Consumption
鈥?Sleep State with Disabled Master Clock
PWM Controller
鈥?Two PWM Signals
Real Time Clock (RTC)
鈥?Time in GPS Format and 15-bit Fractional Part of a Second
鈥?Programmable Interrupt
鈥?Timer with a 8-bit Fractional Part of a Second and Parallel Load
2.3V to 3.6V or 1.8V Supply Voltage
Includes Power Supervisor
Battery Backup Memory
9 mm
脳
9 mm 100-pin BGA Package
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GPS Baseband
Processor
ATR0620
Summary
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Preliminary
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Rev. 4574CS鈥揋PS鈥?5/05

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