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Features

鈥?/div>

PCI 2.1 Compliant

Supports 33/66 MHz Operation

Master and Slave Support 32-bit Address and Data Transfers

Supports Variable Burst Size Transfers

Performs Zero Wait State Transfers

Master Capable of Performing I/O, Memory and Configuration Types of Transfers

Master Supports Byte Mode Operation

Master Capable of Performing Memory Write Invalidate and Memory Read Line

Operations

Performs Back-to-back Transfers

Fully Synchronous Design

Approximately 12K Gates

Slave Supports Up to Six Address Ranges

Verilog-HDL Based Design

Includes Comprehensive Test Environment (complete results listed in this document)

32-bit PCI

ASIC Core

ATPCI-

SSP8000-32

Summary

System Overview

PCI Bus

32-bit

PCI Core

Application

PCI Peripheral

Overview

The ATPCI-SSP8000-32 is a fully synthesizable core that can be implemented in any

Atmel ASIC library (gate array or standard cell). The core is supported by a compre-

hensive PCI test environment that can be used to verify the entire design, including

the application. The PCI Core can be used in any application that requires a 32-bit

master or slave core at either 33 or 66 MHz. The interface to the application consists

of a master interface, a slave interface and a configuration interface.

Rev. 1665AS鈥?7/01

Note: This is a summary document. A complete document is avail-

able under NDA. For more information, please contact your local

1

Atmel sales office.

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ATPCI-SSP8000-32

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