鈥?/div>
AVR 鈥?High-performance and Low-power RISC Architecture
鈥?121 Powerful Instructions 鈥?Most Single Clock Cycle Execution
鈥?32 x 8 General-purpose Working Registers + Peripheral Control Registers
鈥?Up to 6 MIPS Throughput at 6 MHz
Data and Nonvolatile Program Memory
鈥?128K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
鈥?4K Bytes Internal SRAM
鈥?4K Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
鈥?Programming Lock for Flash Program and EEPROM Data Security
鈥?SPI Interface for In-System Programming
Peripheral Features
鈥?On-chip Analog Comparator
鈥?Programmable Watchdog Timer with On-chip Oscillator
鈥?Programmable Serial UART
鈥?Master/Slave SPI Serial Interface
鈥?Real-time Counter (RTC) with Separate Oscillator
鈥?Two 8-bit Timer/Counters with Separate Prescaler and PWM
鈥?Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,
Capture Modes and Dual 8-, 9-, or 10-bit PWM
鈥?Programmable Watchdog Timer with On-chip Oscillator
鈥?8-channel, 10-bit ADC
Special Microcontroller Features
鈥?Low-power Idle, Power-save and Power-down Modes
鈥?Software Selectable Clock Frequency
鈥?External and Internal Interrupt Sources
Specifications
鈥?Low-power, High-speed CMOS Process Technology
鈥?Fully Static Operation
Power Consumption at 4 MHz, 3V, 25擄C
鈥?Active: 5.5 mA
鈥?Idle Mode: 1.6 mA
鈥?Power-down Mode: < 1 碌A(chǔ)
I/O and Packages
鈥?32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines
鈥?64-lead TQFP
Operating Voltages
鈥?2.7 - 3.6V for ATmega103L
鈥?4.0 - 5.5V for ATmega103
Speed Grades
鈥?0 - 4 MHz for ATmega103L
鈥?0 - 6 MHz for ATmega103
鈥?/div>
鈥?/div>
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega103(L)
Summary
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Rev. 0945GS鈥?9/01
Note: This is a summary document. A complete document is
available on our web site at
www.atmel.com.
1
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