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ATL25/484 Datasheet

  • ATL25/484

  • ASIC

  • 14頁

  • ATMEL   ATMEL

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Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
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Available in Gate Array or Embedded Array
High-speed, 100 ps Gate Delay, 2-input NAND, FO = 2 (nominal)
Up to 6.9 Million Used Gates and 976 Pins
0.25碌 Geometry in up to Five-level Metal
System-level Integration Technology
鈥?Cores: ARM7TDMI
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, ARM920T
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, ARM946E-S
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and MIPS64
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5Kf
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RISC
Microprocessors; AVR
廬
RISC Microcontroller; OakDSPCore
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, Teak
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and
PalmDSPCore
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Digital Signal Processors; 10/100 Ethernet MAC, USB, 1394, 1284,
CAN and Other Assorted Processor Peripherals
鈥?Analog Functions: DACs, ADCs, OPAMPs, Comparators, PLLs and PORs
鈥?Soft Macro Memory: Gate Array
SRAM 鈥?ROM 鈥?DPSRAM 鈥?FIFO
鈥?Hard Macro Memory: Embedded Array
SRAM 鈥?ROM 鈥?DPSRAM 鈥?FIFO 鈥?Stacked E
2
鈥?Stacked Flash
鈥?I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB; Output Currents up to 16 mA
@2.5V; 2.5V Native I/O, 3.3V Tolerant/Compliant I/O, 5.0V Tolerant I/O
ASIC
ATL25 Series
Description
The ATL25 Series ASIC family is fabricated on a 0.25碌 CMOS process with up to five
levels of metal. This family features arrays with up to 6.9 million routable gates and
976 pins. The high density and high pin count capabilities of the ATL25 family, coupled
with the ability to add embedded microprocessor cores, DSP engines and memory on
the same silicon, make the ATL25 series of ASICs an ideal choice for system-level
integration.
Figure 1.
ATL25 Gate Array ASIC
Standard
Gate Array
Architecture
Figure 2.
ATL25 Embedded Array ASIC
Standard
Gate Array
Architecture
Analog
1414C鈥揂SIC-08/02
1

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