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ATFI1502AS Datasheet

  • ATFI1502AS

  • High-performance EEPROM CPLD

  • 25頁

  • ATMEL   ATMEL

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上傳產品規(guī)格書

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Features
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High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
鈥?32 Macrocells
鈥?5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
鈥?44 Pins
鈥?7.5 ns Maximum Pin-to-pin Delay
鈥?Registered Operation up to 125 MHz
鈥?Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
鈥?D/T Latch Configurable Flip-flops
鈥?Global and Individual Register Control Signals
鈥?Global and Individual Output Enable
鈥?Programmable Output Slew Rate
鈥?Programmable Output Open Collector Option
鈥?Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
Automatic 10 碌A Standby for 鈥淟鈥?Version
Pin-controlled 1 mA Standby Mode
Programmable Pin-keeper Inputs and I/Os
Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead PLCC and TQFP
Advanced EEPROM Technology
鈥?100% Tested
鈥?Completely Reprogrammable
鈥?10,000 Program/Erase Cycles
鈥?20-year Data Retention
鈥?2000V ESD Protection
鈥?200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
Security Fuse Feature
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High-
performance
EEPROM CPLD
ATF1502AS
ATF1502ASL
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Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D Latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
(鈥淟鈥?versions)
Fast Registered Input from Product Term
Programmable 鈥淧in-keeper鈥?Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
鈥?Input Transition Detection
鈥?Power-down (鈥淟鈥?versions)
鈥?Individual Macrocell Power Option
鈥?Disable ITD on Global Clocks, Inputs and I/O
Rev. 0995J鈥揚LD鈥?9/02
1

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