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3.0V to 5.5V Operating Range
Advanced Low Voltage Electricaly Erasable Programmable Logic Device
User Controlled Power Down Pin Option
Pin-Controlled Standby Power (10
碌A(chǔ)
Typical)
Well-Suited for Battery Powered Systems
10 ns Maximum Propagation Delay
CMOS and TTL Compatible Inputs and Outputs
Latch Feature Hold Inputs to Previous Logic States
Advanced Electrically Erasable Technology
Reprogrammable
100% Tested
High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-Line and Surface Mount Packages in Standard Pinouts
High
Performance
E
2
PLD
ATF22LV10C
Block Diagram
Pin Configurations
Pin Name
CLK
IN
I/O
V
CC
PD
Function
Clock
Logic Inputs
Bidirectional Buffers
(3V to 5.5V) Supply
Programmable
Power Down
CLK/IN
IN
IN
IN/PD
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
TSSOP Top View
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
ATF22LV10C
DIP/SOIC
PLCC
(1)
Top view
Note:
1. For PLCC, pin 1, 8, 15, and 22 can be left unconnected. For superior
performance, connect V
CC
to pin 1 and GND to 8, 15, and 22.
Rev. 0780E/LV10C-E鈥?5/98