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3.0V to 5.5V Operating Range
Advanced Low-voltage, Zero-power, Electrically Erasable Programmable Logic Device
Edge-sensing 鈥淶ero鈥?Power
Low-voltage Equivalent of ATF22V10CZ
鈥淶ero鈥?Standby Power (25 碌A(chǔ) Maximum) (Input Transition Detection)
Ideal for Battery Powered Systems
CMOS- and TTL-compatible Inputs and Outputs
Latch Feature Hold Inputs to Previous Logic States
Advanced EE Technology
鈥?Reprogrammable
鈥?100% Tested
High-reliability CMOS Process
鈥?20-year Data Retention
鈥?100 Erase/Write Cycles
鈥?2,000V ESD Protection
鈥?200 mA Latch-up Immunity
Commercial and Industrial Temperature Ranges
Dual Inline and Surface Mount Standard Pinouts
Inputs are 5V Tolerant
High-
performance
EE PLD
ATF22LV10CZ
ATF22LV10CQZ
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Block Diagram
Pin Configurations
All Pinouts Top View
Pin Name
CLK
IN
I/O
GND
VCC
Function
Clock
Logic Inputs
Bi-directional Buffers
Ground
(3 to 5.5V) Supply
PLCC
IN
IN
CLK/IN
VCC*
VCC
I/O
I/O
TSSOP
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
Note:
TSSOP is the smallest package
of SPLD offering.
DIP/SOIC
4
3
2
1
28
27
26
Note:
For PLCC, pins 1, 8, 15, and
22 can be left unconnected.
For superior performance,
connect VCC to pin 1 and
GND to pins 8, 15, and 22.
IN
IN
GND
GND*
IN
I/O
I/O
12
13
14
15
16
17
18
IN
IN
IN
GND*
IN
IN
IN
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O
I/O
I/O
GND*
I/O
I/O
I/O
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
Rev. 0779J鈥?1/00
1
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