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Description
The 64K x 32-bit cell is an embedded 2-Mbit Flash electrically erasable and program-
mable read only memory with a power supply of 1.8V 鹵10%. The memory is organized
as 1024 pages of 64 32-bit words each. The device uses the Atmel ATC18 0.18 碌m sil-
icon process. For easy reprogrammability, it does not require a high input voltage for
programming: the embedded Flash can be operated with a single 1.8V 鹵10% power
supply.
Re-programming the cell is performed on a page basis: the words to be written (from a
minimum of 1 word to a maximum of 64 words) are loaded into the device and then
simultaneously written into the targeted page after the full page has been erased dur-
ing the auto-erase phase. 2 ms are necessary to erase the page, followed by 2 ms to
write the words, independent of the number of words that are written in parallel into
the targeted page. Thus the write time after the auto-erase varies from a maximum of
2 ms per word if only 1 word is written to a minimum of 32 碌s per word if the entire
page is written at a time. Memory read is allowed during data loading and forbidden
once programming has started. The signal rdybsyn pulses low at the beginning of the
program cycle to indicate that the memory is not ready for a read operation. Program-
ming the entire memory can be done using a full chip erase followed by 1024 page
write without auto-erase. Compared to full-memory programming using auto-erase on
each page, the programming time is reduced by half. At the end of each program
cycle, the rdybsyn signal pulses high to indicate that programming is completed and
the memory available for a new program or read cycle. Reading data out of the device
can be done in an asynchronous and random manner, with 70 ns access time.
Rev. 2680A鈥揅ASIC鈥?1/02
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