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ATC18RHA Datasheet

  • ATC18RHA

  • Rad. Hard 0.18 Um CMOS Cell-based ASIC for Space Use

  • 20頁

  • ATMEL   ATMEL

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Feature
s
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Comprehensive Library of Standard Logic and I/O Cells
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ATC18RHA Core and IO18 pads Designed to Operate with V
DD
= 1.8V +/- 0.15V as Main
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Condition
IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V Environments
Memory Cells Compiled or synthesized to the Requirements of the Design
EDAC Library
SEU Hardened DFF鈥檚
Cold Sparing Buffers
High Speed LVDS Buffers (655Mbps)
PCI Buffers
Predefined Die Sizes to Accommodate Standardized Packages and ESA (European
Space Agency) Multi-project Wafer Services
MQFP Package Up to 352 Pins (336 Signal Pins)
MCGA Packages Up to 625 Pins (593 Signal Pins)
ESD better than 2000V
Assurance Programs Allow:
鈥?Testing Flight Models to ESCC and QML Q & V quality grades
鈥?Monitoring Heavy Ions Latch-up Immunity and Total Dose Capability Better than
100 Krads.
Rad. Hard
0.18 碌m CMOS
Cell-based ASIC
for Space Use
ATC18RHA
Description
The ATC18RHA is fabricated on a proprietary 0.18 碌m, six-metal-layers CMOS pro-
cess intended for use with a supply voltage of 1.8V 鹵 0.15V. Table 1 shows the range
of recommended operating conditions for which Atmel library cells have been
characterized.
Table 1.
Recommended operating conditions
Symbol
Vdd
Vdd3.3
Vi
Vo
Temp
Parameter
DC supply voltage
DC supply voltage
DC supply voltage
DC supply voltage
Operating free air
temperature range
Military
Conditions
Core &
standard IOs
3V interface IO
Min
1.65
3
0
0
-55
Typ
1.8
3.3
Max
1.95
3.6
Vdd
Vdd
+125
Unit
V
V
V
V
擄C
The Atmel cell libraries and memory compilers have been designed and or character-
ized in order to be compatible with each other. Simulation representations exist for
three types of operating conditions. They correspond to three characterization condi-
tion sets defined as follows:
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MIN conditions:
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鈥?T
J
= -55擄C
鈥?V
DD
(cell) = 1.95V
鈥?Process = fast (0.95)
鈥?T
J
= +25擄C
鈥?V
DD
(cell) = 1.8V
鈥?Process = typical (1)
4261B鈥揂ERO鈥?6/05
TYP conditions:

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