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AT91SAM7A3 Datasheet

  • AT91SAM7A3

  • AT91 ARM Thumb-based Microcontrollers

  • 32頁

  • ATMEL   ATMEL

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Features
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Incorporates the ARM7TDMI
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ARM
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Thumb
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Processor
鈥?High-performance 32-bit RISC Architecture
鈥?High-density 16-bit Instruction Set
鈥?Leader in MIPS/Watt
Embedded ICE In-circuit Emulation, Debug Communication Channel Support
256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes
鈥?Single Cycle Access at Up to 30 MHz in Worst Case Conditions
鈥?Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
鈥?Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms
鈥?10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities
32K Bytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed
Memory Controller (MC)
鈥?Embedded Flash Controller, Abort Status and Misalignment Detection
鈥?Memory Protection Unit
Reset Controller (RSTC)
鈥?Based on Three Power-on Reset Cells
鈥?Provides External Reset Signal Shaping and Reset Sources Status
Clock Generator (CKGR)
鈥?Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL
Power Management Controller (PMC)
鈥?Power Optimization Capabilities, including Slow Clock Mode (Down to 500 Hz), Idle
Mode, Standby Mode and Backup Mode
鈥?Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
鈥?Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
鈥?Four External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
Debug Unit (DBGU)
鈥?2-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
Periodic Interval Timer (PIT)
鈥?20-bit Programmable Counter plus 12-bit Interval Counter
Windowed Watchdog (WDT)
鈥?12-bit key-protected Programmable Counter
鈥?Provides Reset or Interrupt Signal to the System
鈥?Counter May Be Stopped While the Processor is in Debug Mode or in Idle State
Real-time Timer (RTT)
鈥?32-bit Free-running Counter with Alarm
鈥?Runs Off the Internal RC Oscillator
Two Parallel Input/Output Controllers (PIO)
鈥?Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
鈥?Input Change Interrupt Capability on Each I/O Line
鈥?Individually Programmable Open-drain, Pull-up resistor and Synchronous Output
Shutdown Controller (SHDWC)
鈥?Programmable Shutdown Pin and Wake-up Circuitry
Four 32-bit Battery Backup Registers for a Total of 16 Bytes
One 8-channel 20-bit PWM Controller (PMWC)
One USB 2.0 Full Speed (12 Mbits per Second) Device Port
鈥?On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
Nineteen Peripheral Data Controller (PDC) Channels
Two CAN 2.0B Active Controllers, Supporting 11-bit Standard and 29-bit Extended
Identifiers
鈥?16 Fully Programmable Message Object Mailboxes, 16-bit Time Stamp Counter
Two 8-channel 10-bit Analog-to-Digital Converter
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AT91 ARM
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Thumb
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-based
Microcontrollers
AT91SAM7A3
Summary
Preliminary
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6042AS鈥揂TARM鈥?3-Dec-04
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.

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