鈩?/div>
PECL/LVDS Compatible Clock Inputs
LVDS Output Format (100
鈩?
3-wire Serial Interface (16-bit Data, 3-bit Address):
鈥?Full or Partial Standby Mode
鈥?1:2 or 1:1 Selectable Data Output Demultiplexer
鈥?Analog Gain (鹵1.5 dB) Digital Control
鈥?Input Clock Selection
鈥?Analog Input Switch Selection
鈥?Binary or Gray Logical Outputs
鈥?Asynchronous Data Ready Reset
鈥?Data Ready Delay Adjustable On Both Channels
鈥?Interlacing Functions:
Offset And Gain (Channel to Channel) Calibration
Digital Fine SDA (Fine Sampling Delay Adjust) On One Channel
Internal Static Or Dynamic Built-in Test (BIT)
Very Low Input Capacitance: 2 pF
Power Supply: 3.3 V (Analog), 3.3 V (Digital), 2.25 V (Output)
LQFP144
Temperature Range:
鈥?鈥淐鈥?Grade: 0擄C < T
A
< 70擄C
鈥?鈥淚鈥?Grade: -20擄C < T
A
< 85擄C
Dual 8-bit
1 Gsps ADC
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鈥?/div>
鈥?/div>
鈥?/div>
AT84AD001B
Smart ADC
鈩?/div>
Preliminary
Performance
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Low Power Consumption: 1.4 W (Typ)
Power Consumption in Standby Mode: 60 mW
1.5 GHz Full Power Input Bandwidth (-3 dB)
SINAD = 46 dB Typ (7.3 ENOB), THD = -60 db, SFDR = - 62 dB
at Fs = 1 Gsps, Fin = 500 MHz
2-tone IMD: -60 dBc Min (499 MHz, 501 MHz) at 1 Gsps
DNL = 0.25 LSB Typ, INL = 0.5 LSB Typ
Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration)
Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration)
Low Bit Error Rate (2.10
-13
) at 1 Gsps
Summary
For more information
please contact
hotline-bdc@gfo.atmel.com
Application
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Instrumentation
Satellite Receiver
Direct RF Down Conversion
WLAN
Description
鈥?/div>
The AD84AD001B is a monolithic low-power (1.4 W typ) dual 8-bit analog-to-digital converter,
designed for digitizing in-phase (I) and quadrature (Q) wide bandwidth analog signals at very high
sampling rates of up to 1 Gsps. The ability to directly interface I and Q signals makes the
AD84AD001B ideal for use in direct satellite demodulation applications or dual channel acquisition
applications (instrumentation).
The AD84AD001B uses an innovative architecture, including an on-chip Sample and Hold (S/H), and
is manufactured with an advanced high-speed BiCMOS process.
鈥?/div>
鈥?/div>
The on-chip 2 S/H have a well matched 1.5 GHz full power input bandwidth, providing excellent
dynamic performance in undersampling applications (high IF digitizing).
A 3-wire serial bus interface provides extra adjustment (standby mode, input range, Gray or binary
coding).
2153BS鈥揃DC鈥?8/03
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