鈥?/div>
Overview
The AT78C5090 is a 2-channel SATA PHY supporting Gen 1 speeds of 1.5 Gbps. The
IP has been designed based on the requirements stated in the Serial ATA Standard,
Rev 1.0a, Jan 2003.
On the transmit path, parallel data is registered, passed through a transmit FIFO to
compensate for phase differences between the link and PHY clocks, 8B/10B encoded
and then passed out via a high speed serializer using a spread spectrum clock. Built-
in flexibility permits bypassing the encoding block in addition to optionally disabling the
spread spectrum clocking. The user can control the transmit buffer output swing and
pre-emphasis levels via direct input signals.
On the receive path, the AT78C5090 performs the serial-to-parallel conversion, using
a high bandwidth clock and data recovery (CDR) block. The recovered data is then
passed through a comma alignment block and an optional 8B/10B decode block
before being passed to the phyCtrl layer via a parallel interface. This interface is syn-
chronous to the recovered clock.
The PHY core has an out of band (OOB) processor. As specified by the Serial ATA
standard, three out of band (OOB) signals are used/detected by the PHY, namely
COMRESET, COMINIT, and COMWAKE. Each of these signals are indicated by a
number of bursts of four ALIGN primitives followed by defined idle periods during
which the differential voltage on the serial line is null. OOB signals are observed by
detecting the temporal spacing between adjacent bursts of activity.
Test functions including BIST, scan, parallel and serial loopback modes are configured
and controlled by the use of direct input signals. Similarly, error/status bits are indi-
cated through direct output signals such as bistErr.
3526AS鈥揘ETST鈥?0/04
Note: This is a summary document. A complete document
is available under NDA. For more information, please con-
tact your local Atmel sales office.
1
2
3
