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16 Multiplier-Accumulators
16 Bit Data and 12 Bit Coefficients, 32 Bit Internal Accuracy
16 Banks of 12 Bit Coefficients
16 Taps at 33 MHz
Up to 32 Taps for Symmetrical or Interleaved Zeroed Coefficient Filters at 33 MHz
Up to 63 Taps for Symmetrical Halfband Filters at 33 MHz
Programmable Decimation by 2, 4, 8 or 16
Cascadable Keeping Symmetry Advantages
Output Gain Multiplier
Programmable Microprocessor Interface
208-pin QFP Package
Programmable
FIR Filter
AT76C002
Description
The AT76C002 FIR filter contains 16 multiplier-accumulators which enable it to imple-
ment a 16th order non-symmetrical FIR filter or a 32nd order symmetrical FIR filter,
operating at 33 MHz. Furthermore, it can be configured to implement a 64th order
filter where the even order coefficients are zero, also running at 33 MHz. The incom-
ing samples are 16 bit coded, the coefficients are 12 bit coded and the internal accu-
racy is 32 bits.
The AT76C002 contains 16 banks of 2 bit coefficients that can be selected in one
clock cycle. These banks can also be used to perform decimation by 2, 4, 8 or 16
using FIR filters from 32 taps up to 256 taps. In decimation mode, the symmetry
capabilities cannot be used.
In order to implement long FIR filters at the highest frequency (i.e. 33 MHz) the circuit
can be cascaded, with no limits except the internal accuracy. Symmetry properties
can be used in cascade mode. This halves the number of cascaded circuits to imple-
ment symmetrical filters.
In order to increase the accuracy of the intermediate results, the AT76C002 includes
an output gain multiplier which enables the whole 12 bit dynamic of the coefficients to
be used. Cascadability cannot be used in decimation mode.
The AT76C002 includes a 16 bit microprocessor interface that can be configured to
be Intel or Motorola compatible.
Applications
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High sample rate digital filtering
Image processing
Video processing
Matrix multiplication
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