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AT572D740 Datasheet

  • AT572D740

  • DIOPSIS 740 Dual Core DSP

  • 22頁

  • ATMEL   ATMEL

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Features
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Dual Core System Integrating an ARM7TDMI餂?ARM
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Thumb
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Processor Core and a
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mAgic DSP for Audio, Communication and Beam-forming Applications
High Performance DSP Operating at 100 MHz
鈥?1 GFLOPS - 1.5 Gops
鈥?10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/subtract, 1 Add, 1 Subtract
Floating and Fixed Point) Allowing Single Cycle FFT Butterfly
鈥?Native Support for Complex Arithmetic and Vectorial SIMD Operations: One
Complex Multiply with Dual Add/sub per Clock Cycle or Two Real Multiply and Two
Add/sub or Simple Scalar Operations
鈥?32-bit Integer and IEEE 40-bit Extended Precision Floating Point Numeric Format
鈥?Large Multi-port Data Register File: 512 Registers Organized in Two 4-input 4-
output 256-register Banks
鈥?Orthogonal VLIW Architecture, Code Compression for Code Size Reduction
鈥?Flexible Addressing Capability: 2 Independent Address Generation Units
Operating on a 16 Registers Address Register File Supporting Programmable
Stride, Circular Pointers and Bit Reversal
鈥?1.7 Mbits of On-chip SRAM:
17 K x 40-bit Data Memory Locations
8 K x 128-bit Program Memory Location, Equivalent to 24K Instructions
鈥?DMA Access to the External Program and Data Memory
鈥?Two Main Operating Modes: Run and System Mode
鈥?Efficient Optimizing Assembler: Allows Easy Exploitation of the Available
Hardware Resources Parallelism
Utilizes the ARM7TDMI餂?Processor Core with 32 K Byte of Integrated SRAM,
Operating at 50 MHz
鈥?Fully-programmable External Bus Interface (EBI)
Maximum External Address Space of 4 M Bytes
Up to 4 Chip Selects
Software-programmable 8/16-bit External Data Bus
鈥?8-channel Peripheral Data Controller (PDC)
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8-level Priority, Individually Maskable Vectored Interrupt Controller
4 External, 20 Internal Interrupt Sources, Including a High-priority, Low-latency
Interrupt Request
鈥?28 Programmable I/O Lines
鈥?8-channel 11-bit Programmable Clock Prescaler Feeding the Timer, Watchdog,
USARTs, SPIs
鈥?3-channel 16-bit Timer/Counter
5 Internal Clock Sources and 3 Configurable Sources (External Source or
Cascaded Timer Configuration)
2 Multi-purpose Output Pins plus 1 Output Dedicated to the ADDA Interface plus
3 Outputs Dedicated to the mAgic DSP
鈥?2 USARTs
2 Dedicated Peripheral Data Controller (PDC) Channels per USART
1 USART Supporting Full Modem Interface
鈥?2 Master/Slave SPI Interfaces
2 Dedicated Peripheral Data Controller (PDC) Channels per SPI
8- to 16-bit Programmable Data Length
4 External Slave Chip Selects for each SPI
鈥?Programmable Watchdog Timer
鈥?ADDA (A/D and D/A Converters) Interface Supporting up to 4 Analog to Digital and
4 Digital to Analog, Stereo 24-bit Converters
鈥?IEEE 1149.1 JTAG Boundary Scan on all Active Pins
Efficient ARM - DSP Interface Based on 1K x 40-bit Dual Ported Shared Memory,
Memory Mapped Register Access, and Interrupt Lines
1.8 V Core Operating Voltage, 3.3 V I/O Operating Voltage
On-chip PLL for 100 Mhz Operation from 25 Mhz Reference Clock
352-ball PBGA Package
DIOPSIS 740
Dual Core DSP
AT572D740
Summary
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7001AS鈥揇SP鈥?3/04
Note: This is a summary document. A complete document
is not available at this time. For more information, please
contact your local Atmel sales office.

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