AT52BR3228AT Datasheet

IC型號(hào)：
AT52BR3228AT
PDF描述：
32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory
文件大?。?/label>
364.98KB
PDF頁(yè)數(shù)：
46頁(yè)
芯片廠家：
ATMEL

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Features

鈥?/div>

32-Mbit Flash and 4-Mbit/8-Mbit SRAM

鈥?/div>

Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package

鈥?/div>

2.7V to 3.3V Operating Voltage

Flash

鈥?/div>

2.7V to 3.3V Read/Write

鈥?/div>

Access Time 鈥?70 ns

鈥?/div>

Sector Erase Architecture

鈥?/div>

鈥?Sixty-three 32K WordSectors with Individual Write Lockout

鈥?Eight 4K Word Sectors with Individual Write Lockout

Fast Word Program Time 鈥?15 碌s

Sector Erase Time 鈥?300 ms

Suspend/Resume Feature for Erase and Program

鈥?Supports Reading and Programming from Any Sector by Suspending Erase of a

Different Sector

鈥?Supports Reading Any Word by Suspending Programming of Any Other Word

Low-power Operation

鈥?12 mA Active

鈥?13 碌A(chǔ) Standby

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

VPP Pin for Write Protection and Accelerated Program/Erase Operations

RESET Input for Device Initialization

Sector Lockdown Support

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

Minimum 100,000 Erase Cycles

鈥?/div>

32-megabit

Flash

+ 4-megabit/

8-megabit

SRAM

Stack Memory

AT52BR3224A

AT52BR3224AT

AT52BR3228A

AT52BR3228AT

SRAM

鈥?/div>

4-megabit (256K x 16)/8-megabit (512K x 16)

2.7V to 3.3V V

70 ns Access Time

Fully Static Operation and Tri-state Output

1.2V (Min) Data Retention

Industrial Temperature Range

Device Number

AT52BR3224A

AT52BR3224AT

AT52BR3228A

AT52BR3228AT

Flash Boot

Location

Bottom

Top

Bottom

Top

Flash Plane

Architecture

32M

SRAM

Configuration

256K x 16

512K x 16

Preliminary

Rev. 3338B鈥揝TKD鈥?/03

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AT52BR3228AT Datasheet

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