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is a synchronous, high-bandwidth Flash
memory fabricated with Atmel鈥檚 high-performance CMOS process technology and is
organized either as 2,097,152 x 16 bits (word mode) or as 1,048,576 x 32 bits (double
word mode), depending on the polarity of the WORD pin (see Pin Function Descrip-
tion Table). Synchronous design allows precise cycle control. I/O transactions are
possible on every clock cycle. All operations are synchronized to the rising edge of the
system clock. The range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high-band-
width, high-performance memory system applications.
The AT49LD3200B will automatically activate the Asynchronous Boot Block after
power-up, whereas with the AT49LD3200, the Asynchronous Boot Block can be acti-
vated through Mode Register Set.
The synchronous DRAM interface allows designers to maximize system performance
while eliminating the need to shadow slow asynchronous Flash memory into high-
speed RAM.
The 32-megabit SFlash device is designed to sit on the synchronous memory bus and
operate alongside SDRAM.
Rev. 1940B鈥?1/01
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