音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

AT40K-PCI Datasheet

  • AT40K-PCI

  • AT40K-PCI [Updated 6/01. 25 Pages] Periperals Component Inte...

  • 277.96KB

  • 25頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

Features
鈥?/div>
pci_mt Function Implementing a 32-bit Component Interconnect (PCI) Interface
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Optimized for AT40K/AT40KAL/AT94K Architecture
Extensive Simulation Testing, Includes Test Vectors
Uses 585 Core Cells
Fully-compliant Design Including:
鈥?32-bit, 33 MHz Operation
鈥?Simplified Local Side (DMA Control Engine) Interface
PCI Master Features:
鈥?Memory Read/Write, One-cycle and Burst
鈥?I/O Read/Write, One-cycle and Burst
鈥?Fully Integrated DMA Engine Including Address Counter Register, Byte Counter
Register, Control and Status Register, Interrupt Status Register
鈥?Zero Wait State PCI Read/Write
PCI Target Features:
鈥?Type Zero Configuration Space
鈥?Parity Error Detection
鈥?Memory Read/Write (1M byte) and I/O Read/Write (512K byte), One-cycle and Burst
鈥?Configuration Registers: Device ID, Vendor ID, Status, Command, Class Code,
Revision ID, Header Type, Latency Timer, One Memory Base Address, One I/O
Base Address, Subsystem ID, Subsystem Vendor ID, Maximum Latency, Minimum
Grant, Interrupt Pin, and Interrupt Line
鈥?/div>
PCI
Master/Target
Core Function
with DMA
AT40K-PCI
IP Core
Description
The pci_mt function provides a solution for integrating 32-bit PCI peripheral devices,
and is fully tested to meet the requirements of the PCI specification. It is optimized for
the AT40K FPGA architecture, enabling the designers to focus efforts on the custom
logic surrounding the PCI interface. The pci_mt macro is intended for use in Atmel鈥檚
AT40K/AT40KAL/AT94K devices with remaining logic resources available for user-
defined local side (DMA control engine) customization.
Compliance Summary
鈥?The pci_mt function is compliant with the requirements specified in the PCI Special
Interest Group鈥檚 (SIG) PCI Local Bus Specification, Rev.2.1.
PCI Bus Signals
The following PCI bus signals are used by the pci_mt function:
鈥?/div>
Input
鈥?Standard input-only signal
鈥?/div>
Output
鈥?Standard output-only signal
鈥?/div>
Bidirectional
鈥?Tri-state input/output signal
鈥?/div>
Sustained tri-state
鈥?Signal that is driven by one agent at a time. An agent that
drives a sustained tri-state pin low must actively drive it high for one clock cycle
before tri-stating it. Another agent cannot drive a sustained tri-state signal any
sooner than one clock cycle after it is released by the previous agent.
鈥?/div>
Open-drain
鈥?Signal that is wire-OR with other agents. The signaling agent asserts
the open-drain signal, and a weak pull-up resistor deasserts the open-drain signal.
The pull-up resistor may take two or three PCI bus clock cycles to restore the open-
drain signal to its inactive state.
Enter
description to
appear in data
book TOC and
tag 鈥淒ata Book
Entry鈥?/div>
Rev. 1083B鈥?6/01
1

AT40K-PCI相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Analog IC
    ETC
  • 英文版
    PHASE CONTROL THYRISTOR
    POSEICO
  • 英文版
    PHASE CONTROL THYRISTOR
    POSEICO [P...
  • 英文版
    EZYTRIGGER
    ETC [ETC]
  • 英文版
    PHASE CONTROL THYRISTOR
    POSEICO
  • 英文版
    PHASE CONTROL THYRISTOR
    POSEICO [P...
  • 英文版
    5K - 50K Gates Coprocessor FPGA with FreeRAM
    ATMEL
  • 英文版
    5K - 50K Gates Coprocessor FPGA with FreeRAM
    ATMEL [ATM...
  • 英文版
    COVER DUST SQ POLY FOR LB/UB SER
  • 英文版
    COVER DUST RND POLY FOR LB SER
  • 英文版
    COVER DUST RECT POLY LB/UB SER
  • 英文版
    BOOT SWITCH TOGGLE HALF
  • 英文版
    ACCY O-RING SEAL FOR MULT SERIES
  • 英文版
    BOOT SILICON NUT WASHER BLACK
  • 英文版
    PROTECTIVE GUARD KB SERIES RECT
  • 英文版
    COVER DUST RECT POLY FOR KB SER
  • 英文版
    BOOT SWITCH TOGGLE FULL BLK
  • 英文版
    BOOT SPLASHPROOF WHT M/P/S SER
  • 英文版
    BOOT SWITCH TOGGLE FULL RED
  • 英文版
    BOOT SWITCH TOGGLE FULL YEL

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！