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AT17LV010-10DP Datasheet

  • AT17LV010-10DP

  • AT17LV010-10DP Advance Information [Updated 7/03. 11 Pages]

  • 11頁

  • ETC

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Features
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EE Programmable 1,048,576 x 1-bit Serial Memory Designed to Store Configuration
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Programs for Field Programmable Gate Arrays (FPGAs)
Very Low-power CMOS EEPROM Process
In-System Programmable (ISP) via Two-Wire Bus
Simple Interface to SRAM FPGAs
Compatible with AT40K Devices
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Programmable Reset Polarity
Low-power Standby Mode
High-reliability
鈥?Endurance: 100,000 Write Cycles
Batch Tested for 10 Krads TID and 70 MeV Latch Up Capability
Operating Range: 3.0V to 3.6V, -55擄C to +125擄C
Available in 400 mils Wide 28 Pins DIL Flat Pack
Space FPGA
Configuration
EEPROM
AT17LV010-
10DP
Advance
Information
Description
The AT17LV010-10DP is a FPGA Configuration EEPROM provides an easy-to-use,
cost-effective configuration memory for Field Programmable Gate Arrays. It is pack-
aged in the 28-pin 400 mils wide FP package. Configurator uses a simple serial-
access procedure to configure one or more FPGA devices. The user can select the
polarity of the reset function by programming four EEPROM bytes. The device also
supports a write-protection mechanism within its programming mode.
Rev. 4265A鈥揂ERO鈥?7/03
1

AT17LV010-10DP相關(guān)型號PDF文件下載

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