鈥?/div>
for Field Programmable Gate Arrays (FPGAs)
Cascadable Read Back to Support Additional Configurations or Future Higher-density
Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in the Space-efficient Surface-mount PLCC Package
In-System Programmable via 2-wire Bus
Emulation of Atmel鈥檚 AT24CXXX Serial EEPROMs
Available in 3.3V 鹵 5% LV and 5V 鹵 5% C Versions
System-friendly READY Pin
Replacement for AT17C/LV002A
Description
The AT17C002A and AT17LV002A (high-density AT17A Series) FPGA Configuration
EEPROMs (configurators) provide an easy-to-use, cost-effective configuration mem-
ory for programming Altera FLEX devices. The AT17A Series is packaged in the
popular 20-lead PLCC and the 32-lead TQFP. The AT17A Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The AT17A Series
organization supplies enough memory to configure one or multiple smaller FPGAs.
Using a feature of the AT17A Series, the user can select the polarity of the reset func-
tion by programming internal EEPROM bytes. The AT17A parts generate their own
internal clock and can be used as a system 鈥渕aster鈥?for loading the FPGA devices.
The Atmel devices also support a system-friendly READY pin. The READY pin is used
to simplify system power-up considerations.
The AT17A Series Configurators can be programmed with industry-standard program-
mers or Atmel鈥檚 ATDH2200E Programming Kit.
FPGA
Configuration
EEPROM
Memory
2-megabit
Altera Pinout
AT17C002A
AT17LV002A
Rev. 2280B鈥?8/01
1