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ASM2P3805X Datasheet

  • ASM2P3805X

  • 3.3V CMOS Dual 1-To-5 Clock Driver

  • 12頁

  • ALSC

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June 2005
rev 0.2
3.3V CMOS Dual 1-To-5 Clock Driver
Features
Advanced CMOS Technology
Guaranteed low skew < 200pS (max)
Very low propagation delay < 2.5nS (max)
Very low duty cycle distortion < 270pS (max)
Very low CMOS power levels
Operating frequency up to 166MHz
TTL compatible inputs and outputs
Inputs can be driven from 3.3V or 5V components
Two independent output banks with 3-state control
1:5 fanout per bank
ASM2P3805X
Where X =D for 133MHz Operation
X =E for 166MHz Operation
"Heartbeat" monitor output
V
CC
= 3.3V 鹵 0.3V
Available in SSOP and QSOP Packages
ASM2P3805X
Functional Description
The ASM2P3805X is a 3.3V clock driver built using
advanced CMOS technology. The device consists of two
banks of drivers, each with a 1:5 fanout and its own output
enable control. The device has a "heartbeat" monitor for
diagnostics and PLL driving. The MON output is identical to
all other outputs and complies with the output specifications
in this document. The ASM2P3805X offers low capacitance
inputs. The ASM2P3805X is designed for high speed clock
distribution where signal quality and skew are critical. The
ASM2P3805X also allows single point-to-point transmission
line driving in applications such as address distribution,
where one signal must be distributed to multiple receivers
with low skew and high signal quality.
Pin Diagram
Block Diagram
OE
A
IN
A
5
OA
1
鈥?OA
5
V
CCA
OA
1
OA
2
OA
3
GND
A
1
2
3
4
5
6
7
8
9
10
20
V
CCB
OB
1
OB
2
OB
3
GND
B
OB
4
OB
5
MON
OE
B
IN
B
IN
B
OE
B
5
OB
1
鈥?OB
5
OA
4
OA
5
GND
Q
MON
A
S
M
2
P
3
8
0
5
X
19
18
17
16
15
14
13
12
11
OE
A
IN
A
Alliance Semiconductor
2575, Augustine Drive
鈥?/div>
Santa Clara, CA
鈥?/div>
Tel: 408.855.4900
鈥?/div>
Fax: 408.855.4999
鈥?/div>
www.alsc.com
Notice: The information in this document is subject to change without notice.

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