AS7C4098-12JIN Datasheet

IC型號：
AS7C4098-12JIN
PDF描述：
5V/3.3V 256K x 16 CMOS SRAM
文件大?。?/label>
235.85KB
PDF頁數(shù)：
10頁
芯片廠家：
ALSC

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January 2005

廬

AS7C4098

AS7C34098

5V/3.3V 256K 脳 16 CMOS SRAM

Features

鈥?AS7C4098 (5V version)

鈥?AS7C34098 (3.3V version)

鈥?Industrial and commercial temperature

鈥?Organization: 262,144 words 脳 16 bits

鈥?Center power and ground pins

鈥?High speed

- 10/12/15/20 ns address access time

- 5/6/7/8 ns output enable access time

鈥?Low power consumption: STANDBY

- 110 mW (AS7C4098)/max CMOS

- 72 mW (AS7C34098)/max CMOS

鈥?Individual byte read/write controls

鈥?Easy memory expansion with CE, OE inputs

鈥?TTL- and CMOS-compatible, three-state I/O

鈥?44-pin JEDEC standard packages

鈥?ESD protection

鈮?/div>

2000 volts

鈥?Latch-up current

鈮?/div>

100 mA

- 400-mil SOJ

- TSOP 2

鈥?Low power consumption: ACTIVE

- 1375 mW (AS7C4098)/max @ 12 ns

- 576 mW (AS7C34098)/max @ 10 ns

Logic block diagram

A12

A13

I/O1鈥揑/O8

I/O9鈥揑/O16

1024 脳 256 脳 16

Array

(4,194,304)

GND

Pin arrangement for SOJ and TSOP 2

44-pin (400 mil) SOJ

TSOP2

I/O1

I/O2

I/O3

I/O4

GND

I/O5

I/O6

I/O7

I/O8

A17

A16

A15

I/O16

I/O15

I/O14

I/O13

GND

I/O12

I/O11

I/O10

I/O9

A14

A13

A12

A11

A10

I/O

buffer

Row Decoder

Control circuit

Column decoder

A10

A11

A14

A15

A16

A17

Selection guide

鈥?0

Maximum address access time

Maximum output enable access time

Maximum operating current

Maximum CMOS standby current

AS7C4098

AS7C34098

AS7C4098

AS7C34098

鈥?/div>

160

鈥?/div>

鈥?2

250

130

鈥?5

220

110

鈥?0

180

100

Unit

1/13/05;

v.1.9

Alliance Semiconductor

P. 1 of 10

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AS7C4098-12JIN Datasheet

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