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AS7C4096-12 Datasheet

  • AS7C4096-12

  • 5V/3.3V 512K X8 CMOS SRAM

  • 9頁

  • ALSC

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January 2005
廬
AS7C4096
AS7C34096
5V/3.3V 512K 脳 8 CMOS SRAM
Features
鈥?AS7C4096 (5V version)
鈥?AS7C34096 (3.3V version)
鈥?Industrial and commercial temperature
鈥?Organization: 524,288 words 脳 8 bits
鈥?Center power and ground pins
鈥?High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
鈥?Low power consumption: STANDBY
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
鈥?Equal access and cycle times
鈥?Easy memory expansion with CE, OE inputs
鈥?TTL-compatible, three-state I/O
鈥?JEDEC standard packages
鈥?ESD protection
鈮?/div>
2000 volts
鈥?Latch-up current
鈮?/div>
100 mA
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
鈥?Low power consumption: ACTIVE
- 1375 mW (AS7C4096) / max @ 12 ns
- 576 mW (AS7C34096) / max @ 10 ns
Logic block diagram
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1
Pin arrangement
s
36-pin SOJ (400 mil)
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
NC
NC
44-pin TSOP 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC
Row decoder
524,288 脳 8
Array
(4,194,304)
Sense amp
I/O8
Column decoder
A10
A11
A12
A13
A14
A15
A16
A17
A18
WE
OE
CE
Control
Circuit
Selection guide
Maximum address access time
Maximum outputenable access time
Maximum operating current
Maximum CMOS standby current
AS7C4096
AS7C34096
AS7C4096
AS7C34096
鈥?0
10
5
鈥?/div>
160
鈥?/div>
20
鈥?2
12
6
250
130
20
20
鈥?5
15
7
220
110
20
20
鈥?0
20
8
180
100
20
20
Unit
ns
ns
mA
mA
mA
mA
1/13/05; v.1.9
Alliance Semiconductor
P. 1 of 9
Copyright 漏 Alliance Semiconductor. All rights reserved.

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