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AS7C34098A-12JCN Datasheet

  • AS7C34098A-12JCN

  • 3.3 V 256 K x 16 CMOS SRAM

  • 10頁(yè)

  • ALSC

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August 2004
廬
AS7C34098A
3.3 V 256 K 脳 16 CMOS SRAM
Features
鈥?Pin compatible with AS7C34098
鈥?Industrial and commercial temperature
鈥?Organization: 262,144 words 脳 16 bits
鈥?Center power and ground pins
鈥?High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
鈥?Easy memory expansion with CE, OE inputs
鈥?TTL- and CMOS-compatible, three-state I/O
鈥?44-pin JEDEC standard packages
鈥?ESD protection
鈮?/div>
2000 volts
鈥?Latch-up current
鈮?/div>
200 mA
- 400-mil SOJ
- TSOP 2
鈥?Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
鈥?Low power consumption: STANDBY
- 28.8 mW /max CMOS
鈥?Individual byte read/write controls
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1鈥揑/O8
I/O9鈥揑/O16
WE
V
CC
1024 脳 256 脳 16
Array
(4,194,304)
GND
Pin arrangement for SOJ and TSOP 2
44-pin (400 mil) SOJ
TSOP2
Row Decoder
I/O
buffer
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
UB
OE
LB
CE
A0
A1
A2
A3
A4
CE
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
Selection guide
鈥?0
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Industrial
Commercial
10
4
180
170
8
鈥?2
12
5
160
150
8
鈥?5
15
6
140
130
8
鈥?0
20
7
110
100
8
Unit
ns
ns
mA
mA
mA
8/17/04, v. 2.1
Alliance Semiconductor
P. 1 of 10
Copyright 漏 Alliance Semiconductor. All rights reserved.

AS7C34098A-12JCN 產(chǎn)品屬性

  • Alliance Memory

  • 4 Mbit

  • 256 K x 16

  • 12 ns

  • 3.6 V

  • 3 V

  • 8 mA

  • + 70 C

  • 0 C

  • SMD/SMT

  • SOJ-44

  • Tube

  • Parrallel

  • 83 MHz

  • 19

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