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AS7C3364NTD32B-200TQIN Datasheet

  • AS7C3364NTD32B-200TQIN

  • 3.3V 64K x 32/36 Pipelined SRAM with NTD

  • 19頁

  • ALSC

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April 2005
廬
AS7C3364NTD32B
AS7C3364NTD36B
3.3V 64K脳32/36 Pipelined SRAM with NTD
TM
Features
鈥?Organization: 65,536 words 脳 32 or 36 bits
鈥?NTD
鈩?/div>
architecture for efficient bus operation
鈥?Fast clock speeds to 200 MHz
鈥?Fast clock to data access: 3.0/3.5/4.0 ns
鈥?Fast OE access time: 3.0/3.5/4.0 ns
鈥?Fully synchronous operation
鈥?Asynchronous output enable control
鈥?Available in 100-pin TQFP package
鈥?Byte write enables
鈥?Clock enable for operation hold
鈥?Multiple chip enables for easy expansion
鈥?3.3V core power supply
鈥?2.5V or 3.3V I/O operation with separate V
DDQ
鈥?Self-timed write cycles
鈥?Interleaved or linear burst modes
鈥?Snooze mode for reduced power standby
Logic block diagram
A[15:0]
16
D
Burst logic
CE0
CE1
CE2
Address
register
Q
16
16
D
16
Q
CLK
Write delay
addr. registers
CLK
16
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
Control
logic
Write Data Registers
CLK
CLK
128K x 32/36
SRAM
Array
DQ [a:d
]
32/36
D
Data
Q
Input
Register
CLK
32/36
32/36
32/36
32/36
CLK
CEN
CLK
OE
Output
Register
32/36
OE
DQ [a:d]
Selection Guide
-200
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
5
200
3.0
375
135
30
-166
6
166
3.5
350
120
30
-133
7.5
133
4
325
110
30
Units
ns
MHz
ns
mA
mA
mA
4/28/05; v.1.3
Alliance Semiconductor
P. 1 of 19
Copyright 漏 Alliance Semiconductor. All rights reserved.

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