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AS7C33512PFD18A-133TQCN Datasheet

  • AS7C33512PFD18A-133TQCN

  • 3.3V 512K x 18 pipeline burst synchronous SRAM

  • 20頁

  • ALSC

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November 2004
廬
AS7C33512PFD18A
3.3V 512K
脳
18 pipeline burst synchronous SRAM
Features
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Organization: 524,288 words 脳 18 bits
Fast clock speeds to 166 MHz
Fast clock to data access: 3.5/4.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous register-to-register operation
Dual-cycle deselect
Asynchronous output enable control
Individual byte write and global write
Available in 100-pin TQFP package
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Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Byte write enables
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
CLK
CS
CLR
Burst logic
Q
19
CS
Address
register
CLK
D
19
17 19
512K 脳 18
Memory
array
18
18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
registers
CLK
D
2
OE
CE
CLK
ZZ
Enable
register
Q
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
鈥?66
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
475
130
30
鈥?33
7.5
133
4
425
100
30
Units
ns
MHz
ns
mA
mA
mA
12/1/04;
v.1.3
Alliance Semiconductor
1 of 20
Copyright 漏 Alliance Semiconductor. All rights reserved.

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