鈩?/div>
architecture for efficient bus operation
鈥?Fast clock to data access: 7.5/8.5/10 ns
鈥?Fast OE access time: 3.5/4.0 ns
鈥?Fully synchronous operation
鈥?Flow-through mode
鈥?Asynchronous output enable control
鈥?Available in 100-pin TQFP
鈥?Byte write enables
鈥?Clock enable for operation hold
鈥?Multiple chip enables for easy expansion
鈥?3.3 core power supply
鈥?2.5V or 3.3V I/O operation with separate V
DDQ
鈥?30 mW typical standby power
鈥?Self-timed write cycles
鈥?Interleaved or linear burst modes
鈥?Snooze mode for standby operation
Logic Block Diagram
A[18:0]
19
D
Address
register
burst logic
Q
19
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
FT
LBO
ZZ
18
CLK
D
Q
19
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
512K x 18
SRAM
array
DQ [a,b]
D
Data
Q
input
register
CLK
18
18
18
18
CLK
CEN
OE
Output
buffer
18
OE
DQ [a,b]
Selection Guide
-75
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
8.5
7.5
280
120
30
-85
10
8.5
260
110
30
-10
12
10
220
100
30
Units
ns
ns
mA
mA
mA
11/8/04, v. 1.1
Alliance Semiconductor
P. 1 of 18
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