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AS7C33512FT18A-85TQIN Datasheet

  • AS7C33512FT18A-85TQIN

  • 3.3V 512K x 18 Flow-through synchronous SRAM

  • 506.82KB

  • 19頁

  • ALSC

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上傳產品規(guī)格書

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November 2004
廬
AS7C33512FT18A
3.3V 512K
脳
18 Flow-through synchronous SRAM
Features
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Organization: 524,288 words 脳 18 bits
Fast clock to data access: 7.5/8.5/10ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous flow-through operation
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
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Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate VDDQ
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
CLK
CS
CLR
Burst logic
Q
19
CS
Address
register
CLK
D
19
17 19
512K x 18
Memory
array
18
18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
CLK
D
registers
Enable
register
2
OE
Q
CE
CLK
ZZ
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-75
8.5
7.5
300
110
30
-85
10
8.5
275
100
30
-10
12
10
250
90
30
Units
ns
ns
mA
mA
mA
11/30/04, v 1.1
Alliance Semiconductor
1 of 19
Copyright 漏 Alliance Semiconductor. All rights reserved.

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