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AS7C33256PFS18B-166TQI Datasheet

  • AS7C33256PFS18B-166TQI

  • 3.3V 256K X 18 pipeline burst synchronous SRAM

  • 19頁(yè)

  • ALSC

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December 2004
廬
AS7C33256PFS18B
3.3V 256K
脳
18 pipeline burst synchronous SRAM
Features
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Organization: 262,144 words 脳 18 bits
Fast clock speeds to 200 MHz
Fast clock to data access: 3.0/3.5/4.0 ns
Fast OE access time: 3.0/3.5/4.0 ns
Fully synchronous register-to-register operation
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
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Individual byte write and global write
Multiple chip enables for easy expansion
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[17:0]
CLK
CS
CLR
Burst logic
18
16
18
18
18
Q
D
CS
Address
register
CLK
256K 脳 18
Memory
array
18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
CLK
D
Byte Write
registers
Byte Write
registers
Enable
register
Q
OE
2
Input
registers
CLK
CE
CLK
ZZ
Output
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ [a,b]
Selection guide
鈥?00
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
5
200
3.0
375
130
30
鈥?66
6
166
3.5
350
100
30
鈥?33
7.5
133
4
325
90
30
Units
ns
MHz
ns
mA
mA
mA
12/10/04; v.1.7
Alliance Semiconductor
P. 1 of 19
Copyright 漏 Alliance Semiconductor. All rights reserved.

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