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AS7C33256NTF18B-80TQCN Datasheet

  • AS7C33256NTF18B-80TQCN

  • 3.3V 256K x 18 Flowthrough Synchronous SRAM with NTD

  • 18頁

  • ALSC

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April 2005
廬
AS7C33256NTF18B
3.3V 256K x 18 Flowthrough Synchronous SRAM with NTD
TM
Features
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Organization: 262,144 words 脳 18 bits
NTD
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architecture for efficient bus operation
Fast clock to data access: 7.5/8.0/10.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous operation
Flow-through mode
Asynchronous output enable control
Available in 100-pin TQFP package
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Byte write enables
Clock enable for operation hold
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
A[17:0]
18
D
Address
register
burst logic
Q
18
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
CLK
D
Q
18
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
256K x 18
SRAM
array
DQ [a,b]
18
D
Data
Q
input
register
CLK
18
18
18
18
CLK
CEN
OE
Output
buffer
18
OE
DQ [a,b]
Selection guide
-75
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
8.5
7.5
260
110
30
-80
10
8.0
230
100
30
-10
12
10
200
90
30
Units
ns
ns
mA
mA
mA
4/13/05, v 1.3
Alliance Semiconductor
P. 1 of 18
Copyright 漏 Alliance Semiconductor. All rights reserved.

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