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AS7C33256NTD32A-166TQIN Datasheet

  • AS7C33256NTD32A-166TQIN

  • 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM with NTD

  • 19頁(yè)

  • ALSC

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November 2004
廬
AS7C33256NTD32A
AS7C33256NTD36A
3.3V 256K脳32/36 Pipelined burst Synchronous SRAM with NTD
TM
Features
鈥?Organization: 262,144 words 脳 32 or 36 bits
鈥?NTD
鈩?/div>
architecture for efficient bus operation
鈥?Fast clock speeds to 166 MHz
鈥?Fast clock to data access: 3.5/4.0 ns
鈥?Fast OE access time: 3.5/4.0 ns
鈥?Fully synchronous operation
鈥?Common data inputs and data outputs
鈥?Asynchronous output enable control
鈥?Available in 100-pin TQFP
鈥?Byte write enables
鈥?Clock enable for operation hold
鈥?Multiple chip enables for easy expansion
鈥?3.3 core power supply
鈥?2.5V or 3.3V I/O operation with separate V
DDQ
鈥?Self-timed write cycles
鈥?Interleaved or linear burst modes
鈥?Snooze mode for standby operation
Logic Block Diagram
A[17:0]
18
D
Address
register
Burst logic
Q
18
CLK
D
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
36/32
Write delay
addr. registers
CLK
Q
18
Control
logic
CLK
Write Buffer
CLK
36/32
256K x 32/36
SRAM
Array
DQ [a:d]
D
Data
Q
Input
Register
CLK
36/32
36/32
36/32
CLK
CEN
CLK
Output
Register
OE
36/32
OE
DQ[a:d]
Selection Guide
-166
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
475
130
30
-133
7.5
133
4
400
100
30
Units
ns
MHz
ns
mA
mA
mA
11/30/04, v. 2.1
Alliance Semiconductor
P. 1 of 19
Copyright 漏 Alliance Semiconductor. All rights reserved.

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