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AS7C331MNTD36A-200TQCN Datasheet

  • AS7C331MNTD36A-200TQCN

  • 3.3V 1M x 32/36 Pipelined SRAM with NTD

  • 441.75KB

  • 18頁

  • ALSC

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上傳產品規(guī)格書

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December 2004
廬
AS7C331MNTD32A
AS7C331MNTD36A
3.3V 1M 脳 32/36 Pipelined SRAM with NTD
TM
Features
鈥?Organization: 1,048,576 words 脳 32 or 36 bits
鈥?NTD
鈩?/div>
architecture for efficient bus operation
鈥?Fast clock speeds to 200 MHz
鈥?Fast clock to data access: 3.2/3.5/3.8 ns
鈥?Fast OE access time: 3.2/3.5/3.8 ns
鈥?Fully synchronous operation
鈥?Asynchronous output enable control
鈥?Available in 100-pin TQFP packages
鈥?Byte write enables
Logic block diagram
A[19:0]
20
D
鈥?Clock enable for operation hold
鈥?Multiple chip enables for easy expansion
鈥?3.3V core power supply
鈥?2.5V or 3.3V I/O operation with separate V
DDQ
鈥?Self-timed write cycles
鈥?Interleaved or linear burst modes
鈥?Snooze mode for standby operation
Address
register
Burst logic
Q
20
CLK
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
32/36
CLK
D
Q
20
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
1M x 32/36
SRAM
Array
DQ[a,b,c,d]
D
Data
Q
Input
Register
CLK
32/36
32/36
32/36
32/36
CLK
CEN
CLK
OE
Output
Register
32/36
OE
DQ[a,b,c,d]
Selection guide
-200
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
12/23/04, V 1.6
-166
6
166
3.5
400
150
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
P. 1 of 18
5
200
3.2
450
170
90
Alliance Semiconductor
Copyright 漏 Alliance Semiconductor. All rights reserved.

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