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AS7C33128PFD36B-200TQI Datasheet

  • AS7C33128PFD36B-200TQI

  • 3.3V 128K X 32/36 pipeline burst synchronous SRAM

  • 19頁

  • ALSC

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February 2005
廬
AS7C33128PFD32B
AS7C33128PFD36B
3.3V 128K X 32/36 pipeline burst synchronous SRAM
Features
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Organization: 131,072 words 脳 32 or 36 bits
Fast clock speeds to 200 MHz
Fast clock to data access: 3.0/3.5/4.0 ns
Fast OE access time: 3.0/3.5/4.0 ns
Fully synchronous register-to-register operation
Double-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
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Individual byte write and global write
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[16:0]
17
CLK
CE
CLR
D
CE
Address
register
CLK
D
Q0
Burst logic
Q1
17
Q
15
17
128K 脳 32/36
Memory
array
GWE
BWE
BW
d
DQ
d
Q
Byte write
registers
CLK
D
DQ
c
Q
Byte write
registers
CLK
D
DQ
b
Q
Byte write
registers
CLK
DQ
a
Q
Byte write
registers
CLK
D
Enable
CE
register
CLK
Power
down
D
Enable
Q
delay
register
CLK
Q
D
36/32
36/32
BW
c
BW
b
BW
a
CE0
CE1
CE2
4
OE
Output
registers
CLK
Input
registers
CLK
ZZ
OE
36/32
DQ [a:d]
Selection guide
鈥?00
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
5
200
3.0
375
130
30
鈥?66
6
166
3.5
350
100
30
鈥?33
7.5
133
4
325
90
30
Units
ns
MHz
ns
mA
mA
mA
1/31/05; v.1.1
Alliance Semiconductor
P. 1 of 19
Copyright 漏 Alliance Semiconductor. All rights reserved.

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