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AS7C3256A-12JIN Datasheet

  • AS7C3256A-12JIN

  • 3.3V 32K X 8 CMOS SRAM (Common I/O)

  • 9頁

  • ALSC

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April 2004
廬
AS7C3256A
3.3V 32K X 8 CMOS SRAM (Common I/O)
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Pin compatible with AS7C3256
Industrial and commercial temperature options
Organization: 32,768 words 脳 8 bits
High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
鈥?Very low power consumption: ACTIVE
- 180mW max @ 10 ns
鈥?Very low power consumption: STANDBY
- 7.2 mW max CMOS I/O
鈥?Easy memory expansion with CE and OE inputs
鈥?TTL-compatible, three-state I/O
鈥?28-pin JEDEC standard packages
- 300 mil SOJ
- 8
脳
13.4 mm TSOP 1
鈥?ESD protection
鈮?/div>
2000 volts
鈥?Latch-up current
鈮?/div>
200 mA
Logic block diagram
V
CC
GND
Input buffer
Pin arrangement
28-pin TSOP 1 (8脳13.4 mm)
28-pin SOJ (300 mil)
A0
A1
A2
A3
A4
A5
A6
A7
I/O7
Row decoder
Sense amp
256 X 128 X 8
Array
(262,144)
I/O0
OE
A11
A9
A8
A13
WE
V
CC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AS7C3256A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
Column decoder
WE
Control
circuit
OE
CE
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A A A A A A A
8 9 10 11 12 13 14
Selection guide
-10
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
10
5
50
2
-12
12
6
45
2
-15
15
7
40
2
-20
20
8
35
2
Unit
ns
ns
mA
mA
4/23/04; v.2.0
Alliance Semiconductor
P. 1 of 9
Copyright 漏 Alliance Semiconductor. All rights reserved.
AS7C3256A

AS7C3256A-12JIN 產(chǎn)品屬性

  • Alliance Memory

  • 32 KB

  • 32 KB x 8

  • 12 ns

  • 3.6 V

  • 3 V

  • 70 mA

  • + 70 C

  • SMD/SMT

  • SOJ-28

  • 25

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